MASSACHUSETTS INSTITUTE OF TECHNOLOGY
LINCOLN LABORATORY
TX-2 TECHNICAL MANUAL
LINCOLN MANUAL NO. 44
Volume 2
JUNE 1961
The work reported in this document was performed at Lincoln Laboratory,
a center for research operated by Massachusetts Institute of Technology,
with the joint support of the U.S. Army, Navy and Air Force under Air
Force Contract AF 19(604)-7400.
LEXINGTON MASSACHUSETTS
CHAPTER 8
PULSE MB LEVEL NOTATION
TABLE OF CONTENTS
-1 INTRODUCTION
-2 REGISTERS AND FLIP-FLOPS
-3 GENERAL PULSE NOTATION
8-3.1 CLOCK PULSES
8-3-2 REGISTER DRIVER PULSES
8-3.3 GATED REGISTER DRIVER PULSES
-k GENERAL LEVEL NOTATION
-5 PULSE AND LEVEL NOTATION EXAMPLES
8-5.1 REGISTER DRIVER PULSES
8-5.2 LEVELS
-6 REGISTER DRIVER LOGIC EQUATIONS
-7 SUMMARY
LIST OF FIGURES
-1 E BIT SYMBOLOGY
-2 E REGISTER SYMBOLOGY
-3 EXAMPLES OF GATED RD PULSES
-k XAS LOGIC
March 1961 8-1
CHAPTER 8
PULSE MB LEVEL NOTATION
8-1 INTRODUCTION
This chapter will discuss the kinds of pulse and level notation used in the following
chapters . This notation is the kind that is found on the TX-2 block schematic drawings .
There are several types of computer notation. However, certain forms of notation appear
over and over again and serve as the basis for the pulse and level notation.
First, all the physical parts of the computer are identified, i.e., the flip-flops, registers,
memories, etc. are given names. These names, wherever possible, are in the form of mnemonic
abbreviations. However, since single letters are used to name registers, the mnemonic
derivation is not always obvious .
Consider a typical build up of names and abbreviations. Normally the P register contains
the address of the next instruction and the Q register the address of the next operand. PK
(the P counter) distributes time levels during the instruction cycle and QK (the Q counter)
distributes time levels during the operand cycle. Now consider the PKLRj^^ register. The
roots of the abbreviation for this register are: PK (P counter), IE (instruction register),
and CF (configuration). A "free" translation of the abbreviation might be: "The register
in which the configuration bits are stored during the instruction cycle."
Once the significance of the PKIE abbreviation is known, it is natural to guess that PKIR^p
is the register in which the operation code bits (OP) are held during the instruction cycle.
Similarly, OKIE is the register in which the operation bits are held during the operand
cycle. In this way a sizeable nomenclature is built up from a relatively small number of
roots .
These names for the registers are in turn used as the roots in naming logical variables whose
truth values depend on the state of associated registers, flip-flops, etc. For example,
PKIR^^ is the name of the logical variable which is "true" (i.e., has the logical value
CF^
"ONE") when the first flip-flop in the PKIP^p register is a ONE. Assuming the significance
of PKIE is known, it is only necessary to understand the effect of adding the subscript
CF
1 and the superscript 1 on the PKIE^^ root to fom a comprehensive understanding of the full
PKIR^^ abbreviation.
CF
The truth value of a variable can be determined in the computer by measuring the voltage on
a wire whose voltage represents this variable, as described in Chapter 3- The relationship
between the variable and the voltage is indicated in the following figure by labeling the
wire with the variable and placing an arrowhead on the wire. If the arrowhead is hollow,
then ground voltage on the wire corresponds to truth value for the variable. Similarly, a
solid arrowhead indicated -3 volts on the wire corresponds to truth value for the variable .
5_2 March I961
o
still another type notation identifies the dynamic processes occurring in the computer.
These processes are usually represented physically ty 0.1 microsecond wide pulses on the
wires which are laheled by this symbology. (Chapter 3 describes these dynamic processes.)
For .example, the following symbology is used to identify the process of jamming the contents
of the PKIE register into the QKIR register and is represented by a 0.1 microsecond wide
negative pulse on the associated wire.
This pulse is usually the output of a register driver. The symbol is interpreted as the RD
pulse which causes the contents of PKIE to be jammed (copied) into the QKIR^p, i.e., the
symbology "names" the pulse. This symbology brings up a convention which should be clari-
fied. Normally the content of a register ( ) is symbolized by
( )
However, what should be symbolized by
is frequently simplified to
PKIR — j — ► QKIP^^
OP ' OP
PKIR^p -^- ^^OP
The jargon used to describe the computer and its operation is based on the types of symbology
just described.
Specifically, this chapter will discuss the notation for:
Register and Flip -Flops
Pulses
Flip -Flop Levels
Logic Wet Levels
RD Logic Equations
8-2 REGISTEIRS AND FLIP-FLOPS
Most of the parts in the computer that are given logical identities are either flip-flops
or assemblages of flip-flops. The assemblages are generally called registers.
March I961 8-3
Normally, the individual flip-flops never have single letter abbreviations. The mnemonics
used to identify the flip-flops gives some hint of their function and sometimes indicates
the type or subclass the flip-flop belongs to. Thus,
ST - STatus control flip-flop found in In-Out control units.
PI - instruction cycle (P) interlock (l) flip-flop. Since there are more than one
of these, the subscript indicates that this is the number three PI interlock.
EB - E register Busy interlock flip-flop. Since there is only one of these, no
subscript is required.
The identification of flip-flops within a register is quite straightforward. The data
registers such as A, B, C, D, E, etc. have ordered quarters and ordered bits within the
quarter. The order reads from right to left. Fig. 8-1 shows the E bit symbology. The i.j
flip-flop in this register, i.e., E. ., is the j-th flip-flop in the i-th quarter.
The counter registers are not quartered, so a single number ordering is sufficient. Most
counters are made up of both an alpha and beta register. These are identical registers
except the flip-flops in one are pulsed by alpha gated clock pulses and the flip-flops in
the other are pulsed by beta gated clock pulses . PK^, and PKg are typical examples of
flip-flops in the alpha and beta PK counter registers, respectively.
8-3 GENERAL PULSE NOTATION
There are three basic types of pulses:
1) Clock pulses.
2) Register driver pulses (gated clock pulses).
3) Gated register driver pulses (the pulse inputs that SET, CLEAR, and COMPLEMENT
flip-flops ) .
8-3.1 CLOCK PULSES. These occur as a train of negative going pulses at 0.^ microsecond
intervals. The P (beta) train of pulses lag the a (alpha) train of pulses by 0.2
microseconds. No identifying distinction is made between one alpha pulse and another
or between one beta pulse and another. The notation for clock pulses is
It is important to realize that the alpha implies an uninterrupted train of alpha
pulses and, sim-ilarly, that the beta implies an uninterrupted train of beta pulses.
-3.2 REGISTER DRIVER PULSES. The pulses from any register driver occur at a specific time
and initiate a specific process. For this reason, the symbol for the register driver
pulse generally indicates, at least partially, the process initiated by the pulse.
Register driver pulses are always negative. Two common types of register driver
pulse notation are used depending on whether the process initiated does or does not
involve an information transfer. Thus,
8-1+ March I961
-^^ — ► E - is a pulse which transfers in some way the content of M
into E.
1— i ^— ► E - is a pulse which SETS ( I ^ » - ) , CLEARS ( I »- ) ,
COMPLEMENTS ( ' — ► ), or PEEMUTES ( ' — 5— ► ) the content
of E.
The following are specific examples of register driver pulses taken from the TX-2
hlock schematics or from the timing charts in Chapter YJ:
M - ► E - copies the contents of those flip-flops in the M register
which contain OKES into the corresponding flip-flops in
the E register, i.e., initiates a OWES transfer.
M ► E - initiates a ZEROS transfer.
— - — ► E - is really the symhol for two register driver pulses having
the same input register driver logic, i.e., hoth register
driver pulses are fired off at the same time even though
they originate from different register drivers. The
pulses initiate a ZEROS-ONES transfer.
j fc. E - initiates a jam (ZEROS, ONES) transfer.
1 c
E
se
M
Sometimes the type of input logic on the register driver producing the pulse is more
completely identified hy a subscript xmder the arrow. The subscript serves the
additional function of hinting at the process in which the register driver pulse is
used. Some specific examples of this are:
- complements E "under sign extension control .
- copies the content of M into E "under permuted activity
a
^ control" . These pulses are used in the configuration
process .
In these examples, the words "sign extension control" and "permuted activity control"
are only meaningful when the person using the synbols has a detailed knowledge of the
sign extension process and the configuration process (in which permuted activity
takes place). These processes are discussed in detail in Chapter 13- Both sign
extension control and permuted activity control take into account the configuration
specified by the instruction. Fracture, activity, and permutation information are
decoded from the configuration (CF) bits and combined with information decoded from
the operation (OP) bits to generate configuration control levels. These levels find
their way into the sign extension and permuted activity control nets. The output
from these nets in turn find their way into the register driver logic initiating the
pulses fired off during these processes.
March 19 6l
Subscripting in the register abbreviations is used to indicate the specific quarters
affected by the pulse. Fig. 8-2 shows how this notation is used in the permutation
process .
8-3.3 GATED REGISTER DRIVER PULSES. These are the pulse inputs to the flip-flops themselves.
Unlike the register driver pulses, these are positive going pulses. Usually these
pulses are not distinguished by a name or notation of their own. They can be iden-
tified by examining the logic on the block schematics that produced them. Fig. 8-3
shows two examples .
d-h GENERAL LEVEL NOTATION
Two basic types of level notation are used: one type identifies levels associated with
flip-flops; the other type identifies levels associated with the output of logic nets. In
the first type a superscript or 1 is used to indicate the truth value of the variable,
e.g., PI*^ or PI^. In the second type the truth values are expressed by abbreviations with
and without overbars, e.g., AEJ is an "Arithmetic Element Jump" level, while AEJ is a "not
Arithmetic Element Jump" level. (The overbar is read as "not".) Logically, the overbar
indicates the converse of the level represented by the abbreviation alone.
8-5 PULSE MD LEVEL NOTATION EXAMPLES
Typical examples of computer pulse and level notation are given below.
8-5.1 REGISTER DRIVER PULSES.
PKTR — - — ► N - if PKIR contains a ONE, its contents are
CF 2.9-1.5 "^ CF
transferred into N . By means of
li .y - -L . 7
this pulse, the sign bit of PKIR^^ is expanded
to fill lU bits in N.
PAD
-2_^N
A ,C - initiates a "partial add" (PAD) which effects
i i
the i-th quarter of the A and C registers.
1^,2,1
clears the 1st, 2nd, and Hh quarter of the N
register.
ND
SELECT - in the In-Out Element, 0.^ microsecond levels
^~ — <> IOC
are pulses, hence the notation. The ND
indicates that the pulse will go only to the
specific 10 unit determined by the output of
the N Decoder, i.e., N determines the sequence,
J
IOC is an abbreviation for " In-Out Control" .
SELECT hints at the function of the pulse.
8-6 March I961
(pi ' PKIR + Pic) — 3 — ^ XAS) - this is a somewhat unusual notation.
Basically^ the truth value of the statement on
the left is copied into the XAS flip-flop.
When either one of the terms in the bracket is
true^ XAS is set to OWE; if both are false ^
XAS is cleared to ZERO. (See Fig. Q-k.)
PK| + 1 ► PK - indexes the PK counter by one^ i.e., one is
added to the contents of the PK counter by the
pulse .
PK + 1 IN- PK - does not index the P counter by one, i.e., the
register driver pulse is not fired off. This
notation is used to indicate inhibitory register
driver logic .
2k 2k
► PK - presets the P counter to the PK time level
state from whatever state it is in.
8-5.2 LEVELS.
A - indicates the content of the i-th quarter of A is "all ONES" .
i
f . - indicates the fracture decoded from the configuration bits. There
are four fractures: f^ (36), f^ (l8,l8), f^ (27,9) and f^ (9,9.9.9)-
FD - indicates the coimt is "finished" in the i-th quarter of D.
i
IV - indicates the sign quarters of the subwords in the Arithmetic Element.
In this case, the roman numeral indicates quarter k is the sign quarter.
QKIR 1 "^ 2 - if either an f or f fracture is specified, this level will be
decoded, during the operand cycle, fran the contents of the QKIR
register.
NP o - is generated by the instruction word (n) parity (P) check circuit.
3o
The subscript indicates that the parity count is taken over 3o bits .
Whether an odd or even (ev) level is generated depends on the parity
of the information in W.
lOCM - is an abbreviation for an in-out-control-mixer level. The superscript
is one of several and hints at the logical function of the level. The
level is associated with the In-Out Element and is boimd on the lOCM
Bus.
March I961
020!
PK - is an alpha PK time decoder.
026 02a
PK - is a beta PK time decoder. It occurs 0.2 microsecond after PK
START
PI 1 - is an interlock level associated with the instruction cycle.
Specifically, it is one of two start interlock levels involved in
the logic for starting the PK counter.
K^^ - is generated when the nximber of the new sequence specified by the
output of the J coder is the same as the number of the current sequence
specified by the contents of the K register.
8-6 REGISTER DRIVER LOGIC EQUATIONS
Boolean algebra equations are used to describe the way in which levels gate pulses in
register drivers .
Consider the equation:
WAIT , 22a 2^0! llCly I 2i^- _ ^
a • PI ■ (PK • ft: + PK • CSK ) = ' ► PK .
V
CLOCK PULSE LEVEL LOGIC
1
RD INPUT LOGIC RD PULSE
OUTPUT
An alpha clock pulse is MDed with assorted level logic. When this level logic is satisfied,
the clock pulse will be gated and given the name I ^ » PK. Note that in this equation both
— UACT 1
the alpha pulse and the PI level are necessary conditions for generating 24- PK. The
The equality sign ( = ) indicates that when one side of the equation is true, the other side
of the equation is also satisfied.
Consider now how the above equation can be broken down into two other equations.
a • PI • P
2
WAIT 23CZ iia — .
2k
a . px'""-^ • pK^-J. • CSK — ' I »► PK
In this case an implication sign ( 3 ) is used instead of an equality sign ( = )• The
fact that the left hand side of the equation is satisfied "implies" that the right hand side
is also satisfied, i.e., the fact that the left hand side of the equation is true is
sufficient to make the right hand side also true. But, in this case the converse is not
true, i.e., the fact that the right hand side of the equation is true is not sufficient to
make the left hand side also true.
March I961
5-7 SUMMARY
It is important to realize that the significance of a given pulse or level lies strictly in
the specific logic that produced it. The notation tries in a systematic vay to hint at this
CH SEQ
logic. E.g., PI can he interpreted as an instruction interlock level calling for a
CH SEQ
change of sequence, but the full significance of PI can only be determined by examining
the logic that produced the level. Similarly, the function of the level can only be
determined by examining all the logic in which the level is used.
March 1961 8-9
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CHAPTER 9
COMPUTED DYNAMICS
TABLE OF CONTENTS
9-1 INTRODUCTION
9-2 INSTRUCTION CLASSIFICATION BY COUNTER ACTIVITY
9-2.1 CLASS A INSTRUCTIONS
9-2.2 CLASS B INSTRUCTIONS
9-2.3 CLASS C INSTRUCTIONS
S-2.k SUB-CLASSIFICATION OF INSTRUCTIONS
9-3 EFFECT OF MEMORIES ON PK AND QK COUNTER ACTIVITY
9-3.1 MEMORY OVERLAP
9-3.2 MEMORY CYCLE TIME
9-3.2.1 PK CYCLES
9-3.2.2 QK CYCLES
9-3.3 EXAMPLES OF ELAPSED INSTRUCTION TIME AS A FUNCTION OF MEMORY LOCATION AND INSTRUCTION
TYPE
9-k SEQUENCE DYNAMICS
9-5 COUNTER DYNAMICS WHEN NO CHANGE OF SEQUENCE (CSK) OR DELAY SYNCHRONIZATION CYCLE(S) ARE
INVOLVED
9-5.1 COUNTER STARTING CONDITIONS
9-5.1.1 pi"™''i
9-5.1.2 Ql"™"
9-5.1.3 START XWK
9-5. l.i^ START FK
9-5.1.5 START AK
9-5.2 SIMPLE PK AND QK WAITING LOGIC
9-6 COUNTER DYNAMICS WHEN A TRANSITION TO OR FROM A CHANGE OF SEQUENCE (CSK) OR DELAY SYNCHRON-
IZATION CYCLE (DSK) is involved
9-6.1 DECISION AND WAITING LOGIC
9-6.2 CSK AND DSK COUNTER STARTING CONDITIONS
9-7 DEFERRED ADDRESSING CYCLES
9-8 IN -OUT TIME CONSIDERATIONS
9-9 PROGRAM EXAMPLE
LIST OF FIGURES
9-1 BASIC INSTRUCTION CLASSIFICATION BY COUNTER ACTIVITY
9-2 INSTRUCTION CLASSIFICATION BY COUNTER ACTIVITY
9-3 EFFECT OF MEMORY OVERLAP AND NO MEMORY OVERLAP SWITCH ON CLASS CI INSTRUCTIONS
9-1+ INFLUENCE OF MEMORIES AND INSTRUCTIONS ON PK AND QK COUNTING CYCLES
9-5 SUCCESSION OF IDENTICAL INSTRUCTIONS WITH INSTRUCTION AND OPERAND WORDS STORED IN DIFFERENT
MEMORIES
March 1961 9-1
9-6 POSSIBILITIES FOR TRMSITIOW FEOM ONE INSTRUCTION TO THE NEXT INSTRUCTION
9-7 STARTING LOGIC FOR PK, QK, XWK, FK AND AK COUNTERS
9-8 PK, XWK, OK AND FK INTERLOCK EVENTS
9-9 SIMPLE WAITING STATE LOGIC
9-10 PI AND CSK, INTERLOCK STATES FOR TRANSITION POSSIBILITIES FROM ONE INSTRUCTION TO THE NEXT
9-11 PK AND DSK DECISION LOGIC
9-12 CSK AND DSK STARTING CONDITIONS
9-13 CSK AND DSK INTERLOCK EVENTS
9-li; DEFERRED ADDRESS CYCLES
9-15 COUNTER ACTIVITY FOR SIMPLE PROGRAM EXAMPLE
9-2 March 19 6l
CHAPTER 9
COMPUTER DYNAMICS
9-1 INTRODUCTION
This chapter will develop a detailed picture of the dynamic operation of the computer. The
occurrence of events^ i.e., pulse inputs to flip-flops, is determined by the occurrence of
counter time levels . Bar graphs will be used to express the dynamic picture of counter
activity. The bar graphs will show the operation and interlocking of the control counters
which generate the time levels .
Two types of dynamic pictures are of interest: one type shows in detail the counter activity
required to execute a specific instruction; the other type takes a broader view and looks at
the counter activity occurring while a sequence of instructions is executed. In the process
of developing these two kinds of pictures the chpater will answer the following types of
questions :
1) During a given instruction, what specific counters will run? When will they
start? How long will they run? What specific time states will the counters
pass through?
2) When, during the execution of the current instruction, can the next instruction
begin? What effect does the memory location of the instruction word and operand
word have on this decision?
3) Where in the current instruction are decisions made that determine whether the
computer will: (a) go on immediately to the instruction in the current sequence,
(b) wait for awhile before going on in the current sequence, (c) change
Immediately to a different sequence, or (d) wait and then change to a different
sequence? What specific factors determine these decisions?
h) What types of decisions does the computer make if the current instruction is held
up because the execution logic requires some part of the computer that is cur-
rently busy with a previous instruction? E.g., what does the computer do if the
Arithmetic Element is tied up executing a MULtiplication at the time an ADD
instruction desires to use the Arithmetic Element?
This chapter will first classify all the operation codes according to the basic counter
activity pattern required by the execution logic of the operation code . This picture
establishes what counters are used by what operation codes and when the counters start with
reference to the running of other counters .
Next, the effect of the memory location of the instruction word and operand word on the
counter activity pattern will be discussed.
A third type picture will show the counter activity pattern for a sequence of instructions .
March 1961 9-3
With these types of general pictures established^, the chapter will then discuss in detail
the logic that specifically determines the pattern of counter activity. First, the starting
logic for each counter will he discussed. Then the logic determining the synchronization
delays and change of sequence processes will he discussed.
The chapter will conclude with an example showing the pattern of counter activity for a
specific sequence of instructions.
Logical definitions and descriptive discussions of the interlock levels used in this chapter
can be found in Chapter 10.
9-2 INSTRUCTION CLASSIFICATION BY COUNTER ACTIVITY.
It is convenient to think of all the instructions as belonging to one of three basic classes,
depending on the use they make of the PK and QK counters. The operation codes determine the
class of instructions in that they determine the use of the counters. The use of the counters,
and the corresponding operation codes are shown in Fig. 19-1.
9-2.1 CLASS A INSTRUCTIONS. These instructions are characterized by having no operand
memory cycle, i.e., a QK cycle does not occur. A further peculiarity of this class
3ia 2^0! 25
is that the PK cycle always terminates in PK , instead of PK . States PK^
through PK are called the "execute instruction", or PKEI states. The execution
logic for the jump instructions, which for the most part make up this class, requires
this PKEI cycle. (Note that all three classes have a mem.ory or PKM cycle which
extends from PK through PK , and an added state PK . )
9-2.2 CLASS B INSTRUCTIONS. These Instructions are like the Class A instructions in that
they have a PKEI cycle. They are imlike the Class A instructions in that an operand
word is obtained from memory during a QK cycle. Except for TSD, these are skip type
instructions. Thus, most Class A and B instructions involve a possible change in
the contents of the P register during the PKEI cycle.
9-2.3 CLASS C INSTRUCTIONS. This class contains the majority of instructions. In these
instructio
a QK cycle
ok
instructions, PK terminates in PK and an operand word is obtained from memory by
9 -2. if SUBCLASSIFICATION OF INSTRUCTIONS. The three classes can be usefully broken down
into subclasses which bring out in greater detail the activity of the PK, QK, FK,
XWK, AK and ASK counters. This has been done in Fig. 9-2.
li+
It should be noted that all instructions, except SKM and OPR, which use XWK at PK
and do not again use XWK, use the contents of the X register for address modification.
Also, all instructions, except FLF, FLG, SPG and SPF, which use FK use the contents
of QKIR for standard configuration control.
CF
9_1]. March 1961
The usual times for starting XWK and FK are PK and QK°°^ respectively.
CLASS A
Class Al (JMP, SKX, JPX, JM.) . The XWK counter is not started until PK^"''
in these Instructions . Note that if PKIR , the execution logic for JMP
CF^
does not require XWK at this time. None of these instructions uses the
FK counter.
Class A2 (lOS). The XWK counter is started at the usual time. PK must
' 25 —
wait in PK for EB in this instruction.
of.
Class A3 (AOP) . AOP starts the AK counter in PK . Because the instruction
uses the Arithmetic Element beginning at PK , PK must vait in PK until
the Arithmetic Element is free^, i.e.^ the AEB condition exists. The last
AK state used depends upon the Arithmetic Element instruction specified
by the AOP.
Class Ak (JOV, JPA^ JNA). This class uses FK;, which can be started at
~T3
PK . FK is started by an interlock start condition^, and might not start
13
immediately at PK . XWK is started at the usual time . PK must wait in
25
PK until the waiting condition is satisfied.
CLASS B
Class Bl (SKM) . XWK is started at the usual time. SKM does not use the
25 ik
FK counter. PK must wait in PK until QK reaches QK .
Class B2 (TSD). XWK and FK are started at the usual times. PK must wait
in PK ^ until QK reaches QK°"^, if Tl}, or QK^*^^ if PI°.
Class B3 (SED). XWK and FK are started at the usual times. PK must wait
25 Ik
in PK -^ until QK reaches QK .
CLASS C
Class CI (LD-, ST-, DPX, ADX, ITA, ITE, UNA, EXA, INS, COM). These are
_ ^^
"typical" instructions in that the PK cycle terminates in PK ; a PK and
a QK cycle occur; and XWK and FK are used and started at the usual times.
2k
Note that QK is loosely interlocked with PK (dashed line). The dashed
2k
line indicates that PK is the earliest time at which QK can begin. It
is possible that QK may not actually start until later when certain other
conditions are satisfied; e.g., QK may not have completed its cycle from
2k
the previous instruction when PK occurs in the current instruction.
March 1961 9-5
Class C2 (SPF^ SPG). XWK is started at the usual time. FK is started at
OK . FK is not used for configuration control. The length of the FK cycle
is detennined by the operation code .
Class C3 (FLF, FLG). XWK is started at the usual time. FK is started at
PKT^ . FK is not used for configuration control. Note that QK is interlocked
with FK and PK.
Class Ck {'DSk, ADD, SUB), This Class is like Class CI, except that the AK
ll|
counter is started at QK
Class C3 (CY-, SC-, W0-, DIV, MUL, TLY) . This class is like Class k, except
that the ASK counter is used as well as the AK counter. AK makes several
iterated subcycles . With the exception of the CYcle and SCale instructions,
the number of subcycles is determined or limited by ASK. (The operation of
the ASK counter is described in Chapters 10 and 1^+.)
Class C6 (AUX, RSX, EXX) . This class is like Class CI, except that an XWK
cycle occurs in the QK cycle as well as in the PK cycle. The interlocks
set by XWK can be the crucial factor determining when the next instruction
can begin.
While Fig. 9-2 shows the general pattern of counter activity for the different classes
of instructions, the specific picture depends on a variety of conditions that will be
pointed out as the chapter develops .
9-3 EFFECT OF MEMORIES ON PK AND QK COUNTER ACTIVITY
The locations in memory of the instruction and operand words have an important effect on
computer timing. This section will examine this effect.
The two basic situations that can exist are: (l) the operand words and instruction words
are stored in the same memory, or, (2) conversely, the operand and instruction words are
stored in different memories. In the first situation no overlap can exist between the
operand and instruction cycles, while in the second situation an overlap is permitted.
9-3.1 MEMORY OVERLAP. Fig. 9-3 shows the effect of memory overlap on Class CI instructions.
It should be noted that "memory overlap" refers to the overlap of the memory cycle
for the next instruction word with the memory cycle for the current operand word, and
not to the overlap of the current operand word with the current instruction word.
In Fig. 9-3(a), the instruction and operand words are stored in different memories.
For this reason, the PK cycle of the next instruction can begin before the QK cycle
of the current instruction ends. In Fig. 9-3(^)); the instruction and operand words
9-6 March 1961
are stored in the same memory (or the No Overlap interlock flip-flop is set to
ONE (no )). Note that a sequence of instruction cycles are conslderahly more
compressed in time in Fig. 9-3(a) than in Fig. 9-3("b) .
9-3-2 MEMORY CYCLE TIME. We shall now examine in some detail the operand and instruction
word cycles. The following general facts should "be kept in mind:
T
1) Each of the four memories^ i.e., S, T, V^^-, and V , have a basic instruction
and operand word memory cycle time. Except for the V memories, the hasic
instruction and operand memory cycles for each memory are the same. How-
ever, the memory cycles differ among the memories. For example, the basic
T Memory cycle is "faster" than the S Memory cycle. Fig. 9-^(a) tabulates
the basic memory cycle times for each memory.
2) The actual elapsed PK and QK time is a function of the instruction itself
as well as the memories used to store the instruction and operand' words .
This is the reason for speaking of a "basic" memory cycle time. The basic
memory time is the time required to read a word out of memory and write the
same word back into memory. Time may be consumed in the PK and QK cycles
performing non-memory functions required by the execution logic of the
instruction. Note that in the case of the PK cycle, this non-memory time
22
always comes after the PKM cycle, i.e., after PK . In the case of the QK
cycle, the non -memory time always comes in the middle of the QKM cycle,
resulting in an "extended" QKM cycle. This time must be added to the basic
memory time. Fig. 9-Mb) and 9-^(c) show the actual PK and QK time levels
required as a function of memories and instructions .
The PK and QK counters proceed by a sort of "hop and skip" process. E.g., once the
PK counter begins counting it hops from state to state because of the PK + 1 PK
register driver pulses. Suppose that the instruction is stored in the S Memory;
PK will hop from PK on up to PK . At PK , inhibitory logic will cause a
PK + 1 PK condition to exist. PK can now proceed only by skipping into a
09
"preset" state. In this case, a 09 PK pulse skips PK into PK ^ . The bold face
states on Figs. 9-Kb) and 9-Mc) indicate the "preset" states of the counter (see
Chapter lO) . Skipping always occurs into these "preset" states. PK now continues
hopping from state to state up to PK . It then skips from PK to PK and
22 24
(usually) then skips again from PK to PK
The rules governing the skipping of counter time states are:
1) All skips are made to preset time states.
2) The skip is always in the forward direction (unless the execution of an
instruction is abandoned and a change of sequence cycle occurs ) .
3) Skips are usually to the next preset state.
March I961 9-7
These rules are not inviolable^ as indicated by the dashed lines on Figs. 9-K'b) and
9-Kc).
9-3.2.1 PK CYCLES. The variations possible during PK cycles are illustrated in
Fig. 9_Ii-(t3). When an instruction word is obtained from memory, PK performs
00 22
the basic memory cycle (PKM) as it runs from PK through PK . The
succession of states followed is determined entirely by the memory involved.
For exajnple, if the instruction word is obtained from the A register, then
a PKM FF cycle is performed which is made up of PK states 00, 01, 02, 09,
10, 11, 12, 13, ih, 15 and 22. Thus the cycle lasts for k.k microseconds.
Different PKM cycles are required by the other memories. If deferred address
words are required by an instruction, then PK will go through similar cycles.
The last deferred address word memory cycle will be followed by one more
final PK cycle which does not use any memory and during which PKA . This
final cycle always uses states 00, 01, 09, 10, 11, 12, 13, 1^, 15 and 22.
After the instruction word memory cycle, if no deferred addresses are
required, or after the final deferred address cycle (the one which does not
use any memory), if deferred addresses are required then PK will attempt to
2U ?2
enter PK from PK" . Two situations can then occur:
1) Interlock conditions may require that the computer abandon the
attempt to execute the instruction and instead perform a change of
22 00
sequence cycle. In this case PK will go from. PK back to PK .
V 02
(A similar situation may arise during any PKM FF cycle at PK .
02 00 V
In this case PK goes from PK back to PK .)
2) On the other hand, PK may have to wait before a decision can be
made as to whether to proceed executing the current Instruction or
to abandon the current instruction, i.e., perform a change of
22 23
sequence cycle. In this situation PK goes from PK to PK and
waits in this state while the delay synchronization counter (DSK)
performs a number of cycles. If, eventually, a change of sequence
p-5 00
cycle occurs, PK will go from PK "^ back to PK . In this case the
Instruction is not executed and is abandoned. On the other hand,
if the Interlock control decides that PK need wait no longer and
no change of sequence is required, then PK will finally proceed
23 2k
from PK to PK .
23 2^4-
In the one case where PK can proceed from PK to PK , and in the other
22
case where interlock conditions permit PK to proceed directly from PK to
2k
PK without any complications, the computer finally reaches a state from
which It can proceed to execute the remainder of the instruction. Up to
this point, all decisions have been made without regard to the class of the
instruction. However, decisions about the succession of counter states are
hereafter strongly Influenced by the class of the instruction.
March I961
9-3-2.2 OK CYCLES. The variations possible during the QKM cycle are illustrated
in Fig. 9-4(c). Note that the QK cycle alvays terminates in QK
The basic QKM cycle for the V memory involves states 00, 01, 02, 03, 09,
10, 11, 13, 1^, 21, 22, 23 and 31. The other memories require different
QKM cycles, which are again further modified by the requirements of the
instruction being executed. In a memory modification type instruction,
such as COM, the basic memory cycle may be "extended" by the insertion of
intermediate states . This allows the word read out of memory to be modified
,- LOAD,
before it is written back into memory. For example, in all non-load (OKIE ;
instructions involving the S and T memories, QKM is extended 0.8 microseconds
2^4- ?5 03
by QK and QK" . QKM can also be lengthened by the QK waiting state
conditions . These can arise only when the operand word is located in the
Vj,jp memory.
9-3.3 EXA14PLES OF ELAPSED BMSTRUCTION TD-iE AS A FLtNCTIOI'I OF MEMOEY LOCATION AJMD INSTRUCTION
TYPE. Three examples will be given illustrating the elapsed time required by a
program consisting of a repetition of identical instructions.
Figs. 9-5(a) and 9-5{'^) show a repetition of LOAD type instructions. In these two
cases the PK cycle time is equal to the PKM time (see Fig. '^-k{a)) plus 0.^ micro-
2k
second for PK , while the QK cycle time is simply the basic QKM time.
In Fig. 9- 5(3-) the instruction words are located in the T Memory and the operand
T S
words are located in the S Memory. In this case (PKM + Q.k) QICM , since
T T
PKM = k.h microseconds and QKM = 6.k microseconds. Note that QK cycles continu-
ously, i.e., QK (which is the normal resting state) lasts only O.k microsecond.
PK, on the other hand, rests in PK at the end of each PK cycle waiting for QK to
occur. Note, also, that the first instruction time (i^-.S microseconds) is shorter
than the succeeding instruction times (6.h microseconds).
In Fig. 9-5(ti) the instruction words are located in the S Memory and the operand
words are located in the T Memory. (The converse of the case shown in Fig. 9-5(a)).
In this case PKM +0.^ QKM , since PKM = 6.h microseconds and QKM = k.k micro-
seconds. Note that in this case, PK cycles continuously, while QK rests in QK
21]-
waiting for PK to occur. Each instruction, including the first one, takes 6.8
microseconds .
The saving in time realized by storing the instruction words in the T Memory and
the operand word in the S Memory, rather than vice versa, is thus approximately O.k
microsecond per instruction. In either case, however, 6.k microseconds is saved
when compared with the case where both instructions and operands are located in the
S Memory.
March 1961 9-9
Fig. 9-5(c) illustrates the case where PKM + OA = QKM , i.e., where the PK and QK
cycles are the same length, by a sequence of IWSert instructions. In the example,
PKM = 6.k microseconds and QKM = 6,8 microseconds. Note that both PK and QK cycle
continuously and that each instruction takes 6.8 microseconds to execute. It can
also be deduced from Fig. 9-^ that a series of INS instructions in which the
instruction words were stored in the T Memory and the operand word were stored in
the S Memory would require 8.8 microseconds per instruction.
9-h SEQUENCE DYNAMICS
Thus far in the chapter counter activity patterns have been established for individual
instructions (or at most for an uninterrupted succession of instructions in the same sequence),
This section will take a broader view and consider all the basic possibilities for getting
from one instruction to the next, and the next instruction in the same sequence or in another
sequence .
Fig. 9-6 shows the four basic possibilities for proceeding from one instruction to the next.
The normal situation is for the current instruction to be followed by another instruction in
the same sequence. By the end of the current PK cycle a definite decision has been made to
continue in the current sequence. As was pointed out earlier in the chapter, this does not
necessarily mean that the next PK cycle will begin as soon as the current PK cycle is
completed, i.e., PK will wait in its resting state, PK , until all the necessary interlock
conditions for continuing are satisfied.
The second possibility is that a decision to change sequence will be made during the current
instruction. The current instruction may or may not be completed before the change of
sequence cycle begins. In any event, the change of sequence cycle cannot begin until the
PK counter is in its PK resting state.
The third and fourth cases result from two different basic situations. Either some inter-
02 23
lock condition has forced the PK counter to wait in PK or PK , or the current instruction
has dismissed the sequence and PK is waiting in its PK resting state until a decision can
be made as to whether to begin another instruction in the current sequence or to change
sequence. During this waiting period a series of delay synchronization cycles are executed
which examine the interlock conditions upon which the decision is based.
In case three, a decision is eventually made to go on in the current sequence. PK will
either complete the current instruction or, if the current instruction has been completed,
begin the next instruction in the current sequence.
In case four, a decision is eventually made to change sequence. If PK is in either the
02 23
PK or PK waiting states, the current instruction will be abandoned. In this case PK
will go back to PK and a change of sequence cycle will occur. If the delay synchroniza-
tion cycle occurs while PK is in PK , the delay synchronization cycle in which the change
of sequence decision is made will simply be followed by a change of sequence cycle, while
00
PK remains in PK
9-10 March 19 6l
9-5 COUNTER DYNAMICS WHEN NO CHANGE OF SEQUENCE (CSK) OR DELAY SYNCHRONIZATION CYCLE(S) (DSK)
ARE INVOLVED
This section -will discuss Case 1 in Fig. 9-6 in detail^ i.e., the case in which a series of
instructions in the same sequence is executed. The counter activity patterns for the
instructions themselves can have any of the forms shown on Fig. 9-2. It is necessary to
examine only the counter starting conditions for PK, QK, XWK, FK and AK to determine the
specific relative starting time of each counter for all the instruction variations. In
order to establish an exact counter activity pattern ;, it is necessary to know ( in addition
to the counter starting conditions) the PK and QK time states used by the instruction and
the time states in PK and QK in which waiting can occur.
Fig. 9_ii. shows the PK and QK time states required as a function of instruction and memory.
^2 25 03
Waiting can occur in PK^ , PK and QK . The conditions under which simple waiting occurs
in these states will he examined in this section. (Waiting can also occur in the 00 resting
state of the PK and QK counters, but this is reflected in the PK and QK counter start
interlock logic . )
9-5.1 COUNTER STARTING CONDITIONS. Fig. 9-7 shows the interlock start conditions for PK,
QK, XWK, FK and AK. In this section, the following assumptions are made:
1) The PI° • CSK? interlock condition is satisfied. PI and CSKj^ are only of
importance when a change of sequence or delay synchronization has just
previously occurred. This will not be the case in this section.
2) All the alarm and pushbutton control conditions are satisfied, i.e., AL,
STARTg. PKS° and PKS°.
Fig. 9-8 shows the times at which the various interlocks involved in the counter
starting conditions are set and cleared. The setting and clearing times are given
as a function of instruction and counter. The time at which an interlock of interest
is set or cleared is given at the intersection of the interlock column and the
instruction row.
Even though all the interlock start conditions are satisfied, a counter will not
start a new cycle until it is in its 00 resting state. Conversely, even though the
counter is in its 00 resting state, it will not start a new cycle until the interlock
start conditions are satisfied.
START
9-5.1.1 PI 1. PK begins coimting when either an instruction word is called
for (PI ) and the PI 1 conditions are satisfied or when a deferred
-1 START
address word is called for (PIg) and the PI 2 conditions are satisfied.
The deferred address situation will be considered a special topic and
discussed at the end of the chapter. The primary interlocks of interest
are PI , XB and QB.
March 19 6l 9-11
PI • CSK, - The assijmption in this section is that this interlock
condition is satisfied.
PI - PI is set during the PK cycle in those instructions that
have an operand (QK) cycle. It is then cleared in the
OK cycle that follows. For most instructions, PI is
00
cleared to ZERO in QK • Some of the instructions that
use the X and F memories for special purposes clear PI
later in the QK cycle. This is done in these cases to
prevent the PK cycle from starting until the current QK
cycle is finished vith the X and F memories .
120;
XB - XB is set in the PK cycle at PK and; in a few
13a
instructions, in the QK cycle at QK . The X write
02a
cycle that follows clears this interlock at XWK
XB predicts that the X register will shortly be free.
PK cannot start until there is assurance (XB ) that the
X Memory will be free at the time that it is required
in the PK cycle .
QB - For those instructions that have an operand (QK) cycle,
QB is set at QK . It is then cleared in these ins true -
31Ct 1
tions at QK . QB prevents the PK cycle from starting
until the current QK cycle is completed unless the
computer is allowed to operate in the memory ove rlap
~S S T — T U — U V T
condition, i.e., NO (P • Q + P 'Q + P "T + P ' Q ).
orpA'prn
The remainder of the logic in the PI 1 level is normally satisfied. It
is covered in detail in Chapter 10.
START
-5.1.2 QI . This is the start interlock level for the QK counter when an
operand word is called for. The primary interlocks of interest are PI
and FI.
1 ^2Ct
PI - This interlock is always set at PK' in those instruc-
1
tions that call for an operand. (See PI discussion
above . )
FI - FI is cleared in the JPA, JOV, JNA, FLF, and FLG
.0
13a
instructions in PK at the time the FK counter is
started. It is then set during the FK cycle. FI
prevents QK from starting if the FK counter is not
available for configuration control during ordinary
operand cycles .
9-12 March 1961
qrpA'Rrn
The remainder of the logic in the QI level is normally satisfied. It
is covered in detail in Chapter 10.
ihcc
9-5.1.3 START XWK. XWK is normally started at PK when the hase address indexing
process occurs . In certain of the jvmp instructions that use the X Memory
31a
for a different purpose ;, XWK is started at PK ;, i.e.^ at the end of the
PKEI phase of the PK cycle. XWK is also started in the AUX, RSX and EXX
instructions during the operand (QK) cycle when the contents of an X Memory
register is "being changed.
9-5.1.1+ START PK. PK is norm_ally started at QK as part of the configuration
control process. In SPP and SPG^ where the F Memory is used for non-
13a
configuration purposes, PK is started at QK . In PLP, PLG, JOV, JPA and
JT^IA, where the P Memory is again used for non-configuration purposes, PK
13CC
is started at PK . In this last case, PK starts hecause PI is cleared at
PK"^ . Note that the E register must he free (EB ) hefore PK starts because
the execution logic of these instructions uses the E register in the same
process in which the P Memory is used.
ito
9-5.1.5 START AK. AK is normally started at QK in those instructions that use
the AK counter in their execution logic. In the AOP instruction, AK is
26a
started at PK
9-5.2 SIMPLE PK AND QK WAITING LOGIC. In addition to the normal waiting that can occur in
02 25
the 00 resting state of the PK and QK counters, waiting can occur in PK , PK and
QK . The interlock logic that causes this waiting is shown on Pig. 9-9. The basic
reason for waiting is that the current cycle of the computer wants to use a part of
the computer that is not currently available. The cycle waits in the "waiting state"
until the cycle can go on. Note in these cases that there is no question of whether
the cycle will or will not go on. The only question is when the cycle can pr oceed.
PK waits in PK if the selected word is located in the E register (PKM PF * VMD )
and either the E register is busy (EB ) or the operand cycle associated with the
previous instruction is not completed (QB )• When the EB * QB condition is satis-
cyocL 02
f ied, PK proceeds to PK . A wait also occurs in PK if the instruction word is
located in the Arithmetic Element (PKM PF * VMD ) and the Arithmetic Element is
02
still performing a previous instruction. In this case PK waits in PK until
AEB • QB occurs. A similar situation occurs in QK . QK cannot go on if the
operand is located in the Arithmetic Element and the Arithmetic Element is busy with
V AE 250;
a previous instruction (QKM FF • VMD ' AEB). Waiting can also occur in PK
when non-operand type instructions (Class A) are executed. The actual waiting state
logic in this case depends on the instruction executed. (See Chapter 17 for a
discussion of the terms used in this logic in each, instruction. )
March I961 9-13
9-6 COUNTER DYNAMICS WHEN A TRANSITION TO OR FROM A CHANGE OF SEQUENCE (CSK) OR DELAY
SYNCHRONIZATION CYCLE (DSK) IS INVOLVED.
This section will discuss in detail Cases 2, 3 and k shown on Fig. 9-6^ i.e.^ the cases
where transitions to or from delay synchronization or change of sequence cycles are involved.
The interlocks that determine these transitions are PI and CSK, . Fig. 9-10 shows the
transition possihilities and the states of PI_ and CSK, required for the transitions to
By examining the conditions which set and clear PI and CSK, ^ it will be possible to
establish the conditions which cause the transitions.
9-6.1 DECISION AND WAITING LOGIC. Certain specific states in the PK cycle are called
"decision states". The following alternative types of decisions are made in these
states:
1) To immediately go on in the current sequence (or, more specifically, in
some cases to go on in the current instruction), subject only to the inter-
lock conditions just described in Section 9-5-
2) To immediately abandon the current instruction and perform a change of
sequence .
3) To wait until the conditions for making a decision to go on with instructions
in the current sequence are available .
k) To wait until the conditions for making a decision to change sequence are
available .
If the decision to wait is made, PK will go into a "waiting state" associated with
the PK "decision state". In this case, the decision to go on in the current sequence
or to make a change of sequence will be made during a delay synchronization cycle(s),
i.e., the decision will now be made by having the DSK counter sample the conditions
on which the decision is based.
Fig. 9-11 summarizes this PK and DSK decision logic. If the instruction word is
02 02
located in the V memory, PK becomes a decision state. Note that at PK , the
FF
instruction word has not yet been placed in the N register. Thus the basic question
on which a decision must be made is whether in fact the instruction word can be read
09
out of memory and placed in N. This will occur if the logic for going on to PK is
satisfied, i.e., if the instruction word is in a register that is currently access-
ible. If this decision cannot be made immediately, CSK, is set to ONE and a delay
02
synchronization cycle(s) occurs. PK waits in PK until DSK clears CSK^ to ZERO.
If at the same time, PI is set to ONE and PK is set back to PK , a change of sequence
9-1^ March I961
cycle will occur. The change of sequence cycle ■will always clear PI so that it can
he folloved by a PK cycle. If PI_ is not set to ONE; PK will wait until the other
OQ
conditions for going on to PK are satisfied (see Sect. 9-5)-
Note in this case that the PK decision state and waiting state are the same^ i.e.;
02
PK . Also note that the current sequence cannot he abandoned until after at least
one delay synchronization cycle occurs .
22
PK is another decision state. Note that in this case the instruction word has
already been placed in the N register. Thus the basic decision is whether to continue
on in the current instruction or to abandon the instruction and perform a change of
sequence . If the "wait" conditions are not generated; PK will inimediately go on to
2h
PK . If the "leave sequence" conditions are generated; PI will be set to ZERO
00
and PK set back to PK ; i.e.; the current instruction will be abandoned ana a change
of sequence will occur. If the "wait" condition occurs ; but the "leave sequence"
23
condition is not generated; CSK, will be set to ONE and PK will wait in PK while
the delay synchronization cycle(s) sample the "wait" and "leave sequence" conditions.
If at some time the "not wait" conditions occur, PK will go on to PK . On the other
hand; if the leave sequence conditions are generated; PI will be set and PK set
00
back to PK ; i.e.; the current instruction will be abandoned and a change of sequence
will occur. Note that the flag of the current sequence can be dismissed (i.e.;
22
lowered) during a TSD in PK . This will occur if the 10 buffer is busy or the QK
cycle of a previous TSD is going on. This decision is made independently of the
status of the hold bit on the TSD.
In PK^"'" all the PKIR instructions (i.e.; all the Class C instructions) will cause
PK to go ahead to PK . If the change sequence conditions are satisfied; PI_ will
be set to ONE in PK . If the instruction has a PKEI cycle; i.e.; is a PKIR
^1 2^
instruction which terminates in PK ; PI„ "will similarly be set in PK (so long as
it is not an lOS instruction). In this case; the instruction will be completed
before the change of sequence called for by the PI condition occurs. The decisions
PS ^1 DIS
made in PK and PK occur only in PKIR type instructions. These instructions
are of two basic types: those that "dismiss" (PKIR ) and those that "do not
dismiss" (PKffi^^^) . Consider first the PKIR class. If the conditions
31
for changing sequence are satisfied in PK ; PI_ -will be set to ONE and the current
~> 00
PK cycle will be followed by a change of sequence cycle when PK reaches PK . If
the conditions for changing sequence are not satisfied; the current instruction
will simply be followed by the next instruction in the current sequence.
DTS REO
Consider now the instructions that can dismiss (PKIR ). While the JX type
instructions are in this class ; the logic requires that they be treated separately
and they will; for the moment; be ignored. If the conditions for dismissing are
25
satisfied in PK ; the flag of the current sequence will be lowered. Note that in
the case of TSD; which falls in this class ; the flag may be dismissed twice during ,
March I961 9-15
the instruction, once in PK and again in PK . In PK a decision will be made to
set CSKk_ to a ONE if the dismiss conditions are satisfied and no sequence requests
attention. This means that the current PK cycle will he followed by a delay synchro-
31
nization cycle( s ) . If the conditions for chaxiging sequence are satisfied in PK ,
PI will be set to OWE and the current PK cycle will be followed by a change of
sequence cycle .
In the case of the JX type instructions, CSK, is set to OEE (if it is to be set) in
pc; 0-1 ^ 2U
PK''^-' instead of PK and the change sequence conditions are sampled only in PK .
Note that, except for the JX and lOS instructions, the change sequence conditions
2h 31 31
are sampled at both PK and PK during those instructions that terminate in PK .
00 2h 25 31
PK is the waiting state associated with the PK , PK and PK decision states.
ota
PI is always cleared during a change of sequence cycle at CSK , i.e., the CSK
cycle is usually followed by a PK cycle. Only when a "trap" occurs on a sequence
meta bit can two CSK cycles occur in succession. See Chapters 10 and 15 . All the
logic for setting and clearing PI and CSK, has now been discussed.
The logical definitions of the factors and terms used on Fig. 9-11 are described in
detail in Chapter 10.
The starting conditions for the CSK and DSK counters will now be examined.
9-6.2 CSK MD DSK COUNTER STARTING CONDITIONS. The interlock start conditions for the DSK
and CSK counter are shown on Fig. 9-12. Note that CSK and DSK are physically the
same counter. Which interpretation is given depends on the state of CSK^^. CSKj^
implies a change of sequence cycle, while CSKj^ implies a delay synchronization cycle.
The interlocks that are set and cleared by the DSK and CSK counter are shown on
Fig. 9-13.
cm A"pm
9-6.2.1 CSI . CSK begins counting when a change of sequence is called for. CSK
cannot start counting until PK is in its PK resting state and CSK^^ is
cleared to ZERO. It is assumed that the START^ pushbutton condition is
satisfied
.0
XW - This interlock is set and cleared in the XVfK coimter cycle.
Since the change of sequence cycle uses the X Memory, the
CSK counter cannot start until XW .
XB - (See discussion earlier under PI l). CSK cannot start while
the X Memory is in use. XB covers such periods until XW .
9 -16 March 19 61
EB - This interlock is set and cleared in the QK cycle ^ except
in the SPG instruction when it is cleared during the FK
cycle. Since the change of sequence cycle uses the E
register for temporary storage, there must he assurance that
the E register is free (EB ) hefore the CSK cycle can start.
PI • CSK, - This interlock condition was discussed earlier in this
U3 ....^
section.
9-6.2.2 DSK STARTING CONDITIONS. DSK begins counting when a delay synchronization
cycle is called for. DSK cannot start coimting unless CSK^^ is set to ONE.
The conditions for CSK, were discussed earlier in this section. DSK will
count only if the XWK coimter is in its 00 resting state and PK is in one
02 23 00
of its waiting states, i.e., PK , PK or PK .
9-7 DEFERKED ADDRESSING CYCLES
When the computer is ready for a new instruction, a PK cycle is used to read the instruction
out of memory. If this instruction calls for a deferred address word, PK goes through
another cycle, during which it reads out the deferred-address word from memory. If this
deferred-address word calls for still another deferred-address word, the cycle is repeated.
Finally, a deferred -address word is obtained which does not call for another deferred-
address word. PK now performs the so-called ultimate deferred-address cycle, during which
the final base address is computed and the index register specified by the instruction word
is nlaced in X.
This section will examine the PK counter activity pattern during the deferred addressing
process. The interlocks of primary interest are PI and PI . The times at which these
interlocks are set and cleared will determine the sequence of cycles.
Fig. 9-1^ shows the basic deferred-address cycle and the times at which PI^ and PI are
set and cleared.
The latest time at which the instruction is strobed into N during a PK cycle is PK" . The
defer bit (N ) is then examined at PK . If a deferred address is called for (N ),
2.9 DFF '- 'y
PI is set to ONE. Assuming the instruction is defined (PKIE ), PI will in turn be set
1 ha 11
to ONE in PK . The conditions (PI^ " Pl^r) ^°^ ^ intermediate -deferred-address cycle to
follow the current PK cycle have now been set up.
Once the instruction word memory cycle (PKM) is completed, PK is ready for an intermediate -
deferred-address cycle. During the instruction word memory cycle, the instruction word's
configuration, hold and OP code bits are placed in the PKIR^^ and PKIR^p registers. This
information will remain in these registers all during the succeeding intermediate and
ultimate deferred cycles .
March 19 61 9-17
START
When the PI 2 conditions are satisfied, the first in temiediate -deferred address cycle
will "begin. These cycles will continue imtil a deferred address word is read out which does
not call for another deferred address word, i.e., N . The latest time at which this occurs
is PKt'''^ ■ N causes PI to be cleared to ZERO in Pk . PI^ insures that PK will execute
2.9 5 5
next an ultimate deferred-address cycle.
The ultimate deferred-address cycle does not involve a memory, but simply the computation
of the final deferred-address. Note that the PI^ ' PI^ interlock condition determines that
130c
no memory cycle is involved. PI^ is cleared to ZERO in PK . The balance of the PK cycle
is then like any normal instruction word cycle. The instruction is completed using the
address computed in the ultimate cycle and the operation called for by the original instruc-
tion word.
9-8 IN-OUT TIME CONSIDERATIONS
Earlier in the chapter the effect of the In-Out Element on the interlocking decisions was
^^WAIT ^^CH SEQ LV SEQ
implicitly examined. For example, the effect of levels like PI , PI , PI ,
etc. on interlock decisions was analyzed. These levels are based on information from the
Sequence Selector. This information, in turn, reflects events that have occurred in the
In-Out Element. However, these events in the In-Out Element are generally initiated by the
central computer. The time between the event in the central computer and the interlock
condition in the central computer that reflects the chain of events in the In-Out Element
initiated by this event can be considerably more than 0.^ microsecond.
Three types of central computer pulses can initiate action affecting the In-Out Element.
These are: (l) lOI clock pulses, (2) lOS mode and select pulses, and (3) TSD data transfer
pulses. A minimum of 1.6 microseconds must elapse before the interlock levels affected by
these piilses can be sampled. The only other events occurring in the In-Out Element that
can affect the central computer are events such as MISIND alarms, EIA alarm levels generated
by switches, etc.
01 12 11
lOI clock pulses can be generated only at PK , PK and CSK . The decision and waiting
states that occur at least 1.6 microseconds after these lOI clock pulses can be used to
sample the interlock conditions affected by these pulses. Note that for this reason a
02
decision to change sequence cannot be made in PK until after at least one delay synchron-
ization cycle occurs, i.e., -until at least 1.6 microseconds has elapsed since PK . Since
22 12
PK occurs at least 1.6 microseconds after PK , a decision to change sequence can be made
22
in PK .
26
The lOS mode and select pulses are generated at PK . These pulses can raise and lower
flags in the Sequence Selector directly or change the mode of the In-Out Element, so that it
PIT QTTQ
in turn changes the status of flags in the Sequence Selector. The PI interlock level
26
affected by these events cannot be sampled until at least 1.6 microseconds after PK . The
31 2^
interlock condition is in fact sampled at PK^ (see Fig. 9-ll)- P-^o ^^ ^°"^ sampled at PK
9-18 March 1961
"by an lOS (see Fig. 9-ll). This sampling is inhibited until after the lOS has a chance to
change the mode of the In-Out Element ^ i.e., -until after PK
The buffer busy level (lOCM ) is used in the "wait" and "leave sequence" logic as well as
22
in the FLAG dismissing logic in PK . This level is affected by the TSD data transfer pulses
that occur in QK • For this reason decisions based on lOCM cannot be made until 1.6
20
microseconds after QK
9-9 PROGRAM EXAMPLE
A specific example of the counter activity that occurs during a short program will be given.
This example is designed to illustrate the effect of the interlock control on computer
dynamics .
The assumption is made that the instruction word is stored in the S Memory and that the
operand is stored in the T Memory. The program will consist of the following instructions:
DSK
CSK
TSD (H^ = hold)
(CF = dismiss requested)
(cf;: = xwK at pk-^ )
DSK
Fig. 9-15 shows the counter activity pattern for this program.
Assume that the initial DSK cycle starts while PK is in the PK resting state (a result of
11
the previous instruction dismissing itself). Assume also that during this DSK cycle, CSK"
samples a SS"^™ -^^ • (K^^ "^^ + KD°°) condition. This condition at CSK^^ causes PI^ to be
set to OWE and CSK, to be cleared to ZERO (see Fig. 9-ll)- This insures that a change of
START
sequence will follow (see Fig. 9-10(b)). Note that all the CSI conditions are now
satisfied, (it is assumed that XW, XB, EB and PI^ were cleared to ZERO previously.)
The CSK cycle clears PI , sets XB and starts XWK (see Fig. 9-13)- XWK in turn clears XB in
XWK°^ (see Fig. 9-8). XB° is the crucial interlock in the PI 1 level. PK starts
counting as soon as XB is cleared.
During the TSD, the PK cycle gets XB" and starts XWK counting. PK also sets PI^ to OWE in
PK^^. All the 01^^^^ conditions are now satisfied (see Fig. 3-k) and QK begins counting.
Note that the conditions that start QK are sufficient, in this case, to start FK counting.
March 1961 9-19
orn/vprp
QK immediately clears PI to ZERO, so that the PI 1 condition is again satisfied. How-
ever, PK must finish the current TSD instruction before beginning the JMP instruction.
If the TSD instruction had dismissed instead of holding, PK may have had to wait in PK
while DSK examined the conditions for going ahead in the program. The fact that the hold
START
bit was a ONE, meant that the PI 1 conditions are Immediately generated and that PK
will go on to the next instruction in the current sequence.
The JMP instruction has no operand cycle. In the case chosen (CF ' CF ), the instruction
31
dismisses. Fig. 9-2 and Fig. 9-8 show that an XWK cycle starts at PK in this instruction.
PK-^ in the JMP instruction sets CSK, to OKE because the PKHC • SS ^ • PKIR
condition is satisfied at that time (see Fig. 9-ll)' 1 CSK, places the CSK counter in
the CSK state, i.e., the DSK resting state. DSK must wait in this state until XWK com-
pletes its cycle and returns to its XWK resting state . At that time delay synchronization
cycles start being executed, and continue until some sequence again requests attention.
9-20 March 19 6l
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CHAPTER 10
COMTROL ELEMENT
TABLE OF COWTEm:S
10-1 IMTRODUCTION
10-2 START-STOP CONTROL
10-2.1 GENERAL DESCRIPTION
10-2.2 START CONTROL
10-2.2.1 AL • AUTO START CONDITION
10-2.2.2 AL • AUTO START CONDITION
10-2.2.3 PB STOP PUSH BUTTON CONDITION
10-2-3 STOP CONTROL
10-2.3.1 LOW SPEED PUSH BUTTON MODE STOP CONTROL
10-2.3.2 LOW SPEED REPEAT MODE STOP CONTROL
10-2.3.3 HIGH SPEED MODE STOP CONTROL
10-2.4 SYTJC SYSTEM
10-2. i^.l OUTPUT CONTROL SWITCHES
10-2.ij-.2 INPUT SELECTION SWITCHES
10-2.5 ALARMS AND ALARM INDICATORS
10-2.5.1 MEMORY SELECTION ALARMS
10-2.5.2 IN-OUT ALARMS
10-2.5.3 OPERATION CODE ALARMS
10-2. 5. Ij- MEMORY PARITY ALARMS
10-2.5.5 MISCELLANEOUS ALARMS
10-2.5.6 ALARM LEVEL (AL)
10-2.5.7 CHIME CONTROL
10-2.5.8 ALARM DELAY COUNTER (ADK)
10-3 INTERLOCKS
10-3.1 GENERAL DESCRIPTION
10-3.2 INSTRUCTION INTERLOCKS
10-3.2.1 INSTRUCTION INTERLOCK^ (PI )
10-3.2.2 INSTRUCTION INTERLOCK^ (PI2)
10-3.2.3 INSTRUCTION INTERLOCK^ (PI )
10-3.2.ij- INSTRUCTION INTERLOCK (PI, )
10-3.2.5 INSTRUCTION INTERLOCK^ (PI )
10-3.3 ARITHMETIC ELEMENT INTERLOCKS
10-3.3.1 ARITHMETIC ELEMENT BUSY INTERLOCK LEVEL (AEB)
10-3.3.2 ARITHMETIC ELEMENT PREDICT INTERLOCK FLIP-FLOP (AEP)
10-3-3 -3 ARITHMETIC ELEMENT INTERLOCK LEVEL (AEI)
10-3.3.^ ARITHMETIC ELEMENT INTERLOCK DURATIONS
10 -3. U MISCELLANEOUS INTERLOCKS
10-3.4.1 E REGISTER BUSY INTERLOCK (EB)
10-3.4.2 Q REGISTER BUSY INTERLOCK (QB)
10-3.4.3 F MEMORY INTERLOCK (FI)
March. I961 10-1
10-3.i^A X REGISTER BUSY INTERLOCK (XB)
10-3. U. 5 X WRITE REGISTER INTERLOCK (XW)
10 -ij- INTERLOCK CONTROL LEVELS
10 -U . 1 INTRODUCTI ON
10-J+.2 PK, QK AMD CSK INTERLOCK START LEVELS
START
10-i+.2.1 INSTRUCTION MEMORY CYCLE INTERLOCK START LEVEL (PI l)
qrp A"prn
IO-J1-.2.2 DEFERRED ADDRESS MEMORY CYCLE INTERLOCK START mVEL (PI 2)
'-START
10-i^-.2.3 OPERAm) MEMORY CYCLE INTERLOCK START LEVEL (QI )
START
10-lj-.2A CHANGE OF SEQUENCE CYCLE INTERLOCK START LEVEL (CSI )
10-il-.3 SEQUENCE CHANGE INTERLOCK LEVELS
nrr QTTQ
10-4.3.1 CHANGE SEQUENCE INTERLOCK LEVEL (PI )
/ AE CH SEQs
10-ij-.3.2 ARITHMETIC ELEMENT CHANGE SEQUENCE INTERLOCK LEVEL (PI )
10-!+. 3. 3 LEAVE SEQUENCE INTERLOCK LEVEL (PI ^J
WAIT
10_lj-.3.l4- INTERLOCK WAIT LEVEL (pi )
10-1)-. 1+ MISCELLANEOUS COUNTER START INTERLOCK LEVELS
lO-i+.i+.l F MEMORY COUNTER START LEVEL ( ' ► FK)
10-l|,i+.2 X MEMORY WRITE COUNTER START LEVEL ( ' ►XWK)
10-1+. 1+, 3 ARITHMETIC ELEMENT COUNTER START LEVEL ( ' »► AK)
10_l|-.lj-.i+ ARITHMETIC ELEMENT STEP COUNTER START LEVEL (ASK I + 1 •►ASK)
IO-I+.I+.5 DELAY SYNCHRONIZATION COUNTER START LEVEL ( ' ^ DSK)
10-5 COUNTERS
10-5.1 GENERAL DESCRIPTION
10-5.2 INSTRUCTION COUNTER (PK)
10-5.3 OPERAND COUNTER (QK)
10-5.4 CHANGE SEQUENCE COUNTER (CSK)
10-5.5 X MEMORY WRITE COUNTER (XWK)
10-5.6 F MEMORY COUNTER (FK)
10-5.7 ALARM DELAY COUNTER (ADK)
10-5.8 ARITHMETIC ELEMENT COUNTER (AK)
10-5.9 ARITHMETIC ELEMENT STEP COUNTER (ASK)
LIST OF FIGURES
10-1 START CONTROL
10-2 STOP CONTROL
10-3 MEMORY SELECTION IN-OUT AND OPERATION CODE ALARMS
10-1+ PARITY ALARMS AND DRIVERS
10-5 MISCELLANEOUS ALARMS
10-6 AL LEVEL LOGIC
10-7 CHIME LOGIC
10-8 ALARM DELAY COUNTER
10-9 PI-, INSTRUCTION INTERLOCK
10-10 PI^ INTERLOCK DURATIONS
10-11 Pip INSTRUCTION INTERLOCK
10-12 PI INSTRUCTION INTERLOCK
10-13 PI, INSTRUCTION, INTERLOCK
10-2 March I961
10-1^ PI^ INSTRUCTION IMEKLOGK
5 5
10-15 Pip MD PI INTERLOCK DURATIONS VS. PK CYCLE
10-16 ARITHMETIC ELEMENT INTERLOCK LEVELS
10-17 AEP ARITHMETIC ELEMENT PREDICT INTERLOCK
1 AK
10-18 AEB;, AEI AND AEP INTERLOCK DURATIONS ON QKTR INSTRUCTIONS
•\ OPR AF
10-19 AEB^ AEI AND AEP INTERLOCK DURATIONS ON PKTR INSTRUCTIONS
10-20 EB EXCHANGE ELEMENT BUSY INTERLOCK
10-21 QB INTERLOCK
10-22 QB"^ AND EB"'' INTERLOCK DURATIONS
10-23 FI CONFIGURATION INTERLOCK
10-2^ XB INDEX REGISTER BUSY INTERLOCK
10-25 X¥ INTERLOCK
10-26 INTERLOCK START LEVELS
10-27 INTERLOCK LEVELS
10-28 FK COUNTER START LEVEL
10-29 XWK COUNTER START LEVEL
10-30 AK START AND ASK - COUNT LEVEL LOGIC
10-31 DSK COUNTER START LEVEL
10-32 PK INSTRUCTION COUNTER (MEMORY SECTION)
10-33 PK INSTRUCTION COUNTER (INSTRUCTION SECTION)
10-3if QK OPERAND COUNTER (MEMORY SECTION)
10-35 QK OPERAND COUNTER (INSTRUCTION SECTION)
10-36 CSK AND DSK CYCLES IN CSK COUNTER
10-37 CSK CHANGE SEQUENCE COUNTER
10-38 XWK INDEX WRITE COUNTER
10-39 FK CONFIGURATION COUNTER
10-iiO FK COUNTER
10-ij-l AK REGISTER LOGIC
10-42 ASK SHIFT REGISTER LOGIC
March I961 10-3
CHAPTER 10
COIWROL ELEMENT
10-1 imRODUCTIOW
This chapter "will disc\iss the logical design of the Control Element. Chapter 6 gave brief
ftinctional descriptions of most of the components in the Control Element and indicated how
the Control Element itself was related to the rest of the computer, l^hile this chapter is
organized in much the same way as Chapter 6, i.e., it covers the following general topics:
Start -Stop Control
Interlocks
Interlock Levels
Counter
It is unlike Chapter 6 in that it deals with these topics at the level of TX-2 Block
Schematic information.
This chapter is also complementary to Chapter 9 which discusses the dynamics of the
computer in terms of counter interlocking.
An elementary view of the needs the Control Element fills is given in Chapter 5^ which
discusses in broad terms the general timing and control problem.
10-2 STAET-STOP COMKOL
10-2.1 GENERAL DESCRIPTION. The output of the Start-Stop Control is a set of levels which
enter into the interlock start level logic.
The Start-Stop Control system is divided into two subsystems: (l) a start control,
and (2) a stop control.
The start control takes into account the factors which influence whether or not
the computer runs, i.e., the state of the start-stop buttons on the console, and
the condition of the alarms and the alarm suppress buttons. (The alarms, alarm
controls, and the alarm delay counter (ADK) will be discussed in Section 10-2. 5.)
The stop control takes into accoimt the factors which influence the effective speed
of operation of the computer, i.e., the modes of operation (high speed, low speed
and low speed repeat), and the various stop buttons and switches.
The start system generates a level which is used by all the interlock start levels.
The stop system generates individual levels for each of the interlock levels.
10 -i|- March 1961
10-2.2 START CONTROL. The start control system is shown In Fig. 10-1. It consists
primarily of two flip-flops that are used as a synchronizer. These flip-flops are
START and START .
STARTS is a necessary condition for the generation of the interlock start levels.
¥nen the PB START pialse is generated, the START flip-flop will be set to OHE if
the ADK counter is in its resting state. (ADKr indicates that no alarm conditions
exist.) The START flip-flop is then synchronously set to OHE after the START
flip-flop is set, again providing that the ADK counter is in its ADK resting
state .
The START flip-flop is cleared when the PB STOP push button is actuated or when
the AL • AUTO START condition exists. The START flip-flop is cleared when the
START flip-flop is cleared or when the AL condition exists. AL indicates an alarm
condition is present. (See Sect. 10-2. 5. 6.)
Note that in all cases the START flip-flop changes state synchronously with the
q; (alpha) timing pulses.
10-2.2.1 AL • AUTO START CONDITION. Wien the START pulse is generated (see Fig.
10-1), the START^ flip-flop is set. At the next a timing pulse, the
START^ flip-flop will be set. With both START flip-flops set, the
computer will operate. If both the AL and AUTO START le|vels exist, then
both the START^ and START^ flip-flops will be cleared. In this situation
the computer will not start again imtil the alarms which generated AL
have been cleared and the START push button is pressed again.
10-2.2.2 AL • AUTO START CONDITION. If when both START flip-flops are set the AL
and AUTO START levels occur, only the START^ flip-flop will be cleared.
This stops the computer, but leaves the START flip-flop set. This
condition continues to exist until the ADK counter returns to ADK^*^. At
that time, the START^ flip-flop is set again. This permits the computer
to restart automatically after a delay equal to the duration of the
operation of the ADK counter cycle.
10-2.2.3 PB STOP PUSH BUTTON CONDITION. If, while the START flip-flops are set,
the PB STOP push button is actuated, the START flip-flop will be cleared.
At the next a timing pulse, the START^ flip-flop will also be cleared
and the computer will stop running.
March I961 10-5
10-2.3 STOP CONTROL. The stop control system is shown in Fig. 10-2. It consists primarily
of two flip-flops used as a synchronizer. These flip-flops are STOP^ and STOP^-
The system also includes the push button mode flip-flops, and the four flip-flops
which stop or prevent an operand (QKB), change of sequence (CSKS), instruction
(PKS ) and/ or a deferred address (PKS ) cycle from starting. The condition of
these "stop" flip-flops determines which mode the computer will stop in when the
computer is running.
The STOP flip-flop is set when the PB STAET push button is actuated and the ADK
counter is in its ADKT resting state. The STOP flip-flop is then cleared by an
1 1
a pulse after both the STOP and STARTp conditions occur and certain other conditions
are satisfied. These other conditions are that either the computer is not in the
Low Speed Repeat (LSR) mode, or, if it is, that a Low Speed Oscillator (LSO) level
is present. STOP^ clears all of the stop flip-flops, i.e., CSKS, QKS, PKB^ and
PKSg.
The STOP_ flip-flop is set by an Ct pulse as soon as it is cleajred if the computer
^ 1
is in either low speed mode. STOP- sets those stop flip-flops that have corre-
sponding stop toggle switches on the console actuated. Since the stop flip-flops
enter into the interlock start levels and inhibit these levels when they are set,
it is clear that the stop system affects the operation of the computer only when
it is in the low speed mode.
The mode of operation flip-flops are set by actuating push buttons on the console.
10-2.3.1 LOW SPEED PUSH BUTTO]^ MODE STOP CONTROL. When the low-speed-push -button-
mode push button is actuated, the LSPB flip-flop is set. Note that STOP
will be set at this time if it was previously clear. If the PB START
push button is then actuated, the STOP and START flip-flops will be
set. The following events will then be initiated by a succession of a
pulses:
a - START flip-flop set
Q: - STOPg flip-flop cleared
a - All stop flip-flops and STOP^ cleared
OC ^ - The one interlock start level which has been generated
n+3
allows the corresponding counter to start. At the same
time, all the stop flip-flops are set which have the
corresponding STOP switches set.
Thus the interlock start levels which correspond to the set STOP switches
are inhibited. The counters corresponding to the interlock start levels
cannot then be started until the START button is again actuated.
10-6 March I961
10-2.3-2 LOW SPEED REPEAT MODE STOP CONTROL. 'Wlien the low- speed-repeat -mode push
button is actuated, the LSR flip-flop is set. Mien the START push button
is then pressed, the operation of the computer is identical to the Low
Speed Push Button mode, except that STOP will not be cleared until an
LSO level occurs and that STOP will not be immediately cleared by the
next a p-ulse. The result is that STOP is cleared for 0.4 microsecond
whenever an LSO level occurs and that O-k microsecond later all the stop
flip-flops are cleared for O.k- microsecond. Immediately afterwards those
stop flip-flops are set which correspond to set stop switches. The
computer is hence able to run only until it tries to use an inhibited
counter cycle. Since START- remains set until the STOP push button is
actuated, the computer is essentially started every time the LSO level
occurs.
Low Speed Oscillator (LSO) . The low speed oscillator consists of
two variable delay units, LSO^ and LSO , coupled together so as to
form an oscillator. When one unit turns itself off, it turns the
other unit on. The two units are each set to be on for approximately
the same amount of time. Although the two units as coupled together
tend to oscillate by themselves, one of the units (LSO ) is set
whenever the Low Speed Repeat push button is pressed in order to
guarantee oscillation. The output LSO level is generated once each
complete cycle by the LSO]_ • LSOp condition. The frequency of
oscillation can be varied over the range 0-500KC by two knobs on
the console.
10-2.3.3 HIGH SPEED MODE STOP COMTROL. The inputs to the LSR and LSPB flip-flops
are arranged so that both flip-flops cannot be set at the same time. If
both flip-flops are set when the power is turned on, the LSR flip-flop
will be cleared by the first a p-ulse that occurs. If one flip-flop is
set and the corresponding mode push button is pressed, both flip-flops
will end up cleared. If one flip-flop is set and the push button for the
other is pressed, then the first flip-flop is cleared and the other is
set. If one flip-flop is set, then the computer is said to be in the
corresponding low speed mode. If neither is set, then the computer is
said to be in the high speed mode. When the computer is in the high
speed mode and the PB START push button is actuated, the STOP and
START flip-flops are set. The following events will then be initiated
by a succession of CC pulses:
a^ - START is set
°^n+l " STOP is cleared
March I961 10-7
a _^P - The stop flip-flops CSKB, QKS, PKB^ and PKB^ are
cleared. These stop flip-flops remain cleared and the
operation of the computer is under control of the
STARTg flip-flop.
10-2. ij- SYNC SYSTEM. The Sync System provides the computer operator with a means of
generating a pulse when certain specified states occur in parts of the computer.
These states are specified by the position of selection switches on the Sync
System control panel. The control panel and the computer console contain other
switches which determine what effect the output pulses from the Sync System will
have.
10-2.4.1 OUTPUT COMTROL SWITCHES. There are two sets of 31 selection switches on
the Sync System control panel. Each set gates the same set of 31 input
levels, but permits the operator to choose two different combinations
of the levels. All the input levels selected by each set are separately
"AND"ed. The two results are then "OR"ed in several ways to generate
output pulse. Thus, if the input levels are designated by L^, ..., L ,
and the two sets of selection switches are designated by S^, . . . , S ,
and T , . . . , T then the logical quantities
and
are formed.
h - (^i^v ••• ^VV
^2 = (^l^^l^ ••■ ^VV
An output pulse from the system can be used to stop the computer. Two
different switches on the computer console, SYNC STOP^ and SYNC STOP^,
determine, via two SYNC STOP flip-flops, which of the above two quantities
will stop the computer. Specifically, the quantity
SYNC STOP = SYNC STOP^ • A^ + SYNC STOP^ • A^
is used to clear the START synchronizer and to generate a SYAL. After
such an alarm the computer can be restarted by pressing the CALACO
button.
The output pulse from the Sync System can also be used to sync test
oscilloscopes. In this case two switches, called SELECTED SYNC^ and
SELECTED SYNC determine directly which of the above two quantities will
generate a sync pulse. Specifically, the quantity
SELECTED SCOPE SYNC = SELECTED SYNC ■ A^
+ SELECTED SYNC^ • A^
10-8 March I961
is sent to varloiis output BNC connectors on the main horizontal bar of
the computer frame. The sync input to a test scope can then be easily
connected so as to receive a sync puLse when specified states occur in
the computer.
One of the output BNC connectors is connected directly to the Trap
Sequence (No. k2 (o)). An output pulse can then be used to raise the
flag of the Trap Sequence, as described in Chapter 15-
10-2. i|. 2 INPUT SELECTION SWITCHES. Sixteen of the thirty-one switches in each
set of selection switches gate levels received from BNC connectors of
the main horizontal bar of the computer frame. These levels are called
\' \' ^1^ ^2' \' \' \' \' '^1' ^2.' ^V ^2' ^3' ^\' ^^\' ^^
lOIp, where the names indicate the section of the frame of the computer
which contain the BNC connectors.
The other fifteen inputs correspond to wired in nets which detect
coincidence between the state of a particular part of the computer and
a corresponding set of toggle switches on the Sync System control panel.
These fifteen inputs are Pi^, PK^^ (PKIR^p), PK^^ (PiaR^^), PK^ (PPCERg),
P, QK^, QKqp (QKTRqp), Q, N^_^q, Mj^_^q, N^, AK^, AK^^ (AKTR^p), ASK and
Xp Q. For example, a coincidence net determines whether the five PK
flip-flops agree in value with the settings of the five PK toggle
switches. If so, then the corresponding input level to the selection
switches is generated.
All fifteen of these nets are similar, aside from the number of switches
and flip-flops involved, except for N. and Mi . In these two cases
the additional switches are somewhat redundant since only the "ONE" value
of the corresponding flip-flop can be detected by the coincidence net.
Note, however, that either state of X can be selected.
10-2.5 ALARMS AND ALARM INDICATORS. The general function of the various alarms was
described in Chapter 6. In addition to the alarm flip-flop indicators, each alarm
has an associated flashing indicator, which flashes each time the corresponding
alarm condition occurs. The flashing indicators are variable delay units which
clear themselves automatically after a 70 milliseconds delay. The clearing logic
for the alarm flip-flops, as well as the logic for generating the alarm conditions,
is shown on Figs. 10-3^ 10-ij- and 10-5-
An alarm flip-flop (and the associated flashing indicator) is set immediately when
the corresponding alarm condition is generated. However, individual alarm
suppression switches in the console determine whether the alarm conditions affect
the operation of the computer.
March I961 10-9
All suppressed alarms are cleared when the PB Clear Suppressed Alarms push button
is pressed. The pulse generated by the button sets a variable delay unit, CA^,
which generates a O.i^- microsecond level. This level is AM)ed with the console
alarm suppress switch levels to clear the corresponding alarm flip-flops. For
example, PSAL is cleared by a • CA^ ' PSAL^^. In this way all the suppressed
alarms are cleared simultaneously.
All unsuppressed alarms are cleared when the Alarm Delay Counter (ADK) reaches
state ADK:^°. For example, PSAL is cleared by a • ADk'"^ • PSAl^. The occurrence
of any unsuppressed alarm causes the generation of the AL level. AL stops the
computer and starts ADK. When ADK reaches state ADK , it will not proceed to
state ADK unless one of the following two conditions are satisfied:
1) The AUTO START switch is turned on.
2) The PB Clear Unsuppressed Alarms push button is pressed.
The presence of the AUTO START level permits ADK to proceed throiigh state ADK to
state ADK , whereupon the computer is promptly allowed to restart. On the other
hand, if the AUTO START switch is not turned on, so that the computer stops, and
the PB Clear Unsuppressed Alarms is pressed, then the CA.^ flip-flop will be set.
The next OL pulse after CA^ is set will clear both CA^ and ADK^ . The computer then
proceeds as in the first case. Note that CA^ acts as a synchronizer so that ADK
will not be affected by the pulse generated from the push button except when ADK
is in state ADk .
10-2.5.1 MEMORY SELECTIOIT ALARMS. (See Fig. IO-3.)
P Memory Cycle Selection Alarm (PSAl) . The PSAL flip-flop is set
whenever a memory cycle is performed in which P is used as the
memory address register and the address in P does not refer to any
of the mem ories logically connected to the computer at the time
(PKM^ ). The alarm occurs at Pk during instruction cycles.
Q Memory Cycle Selection Alarm (QSAL) . The QSAL flip-flop is set
whenever a memory cycle is performed in which Q is used as the
memory address register and the address in Q does not refer to any
of the memories logically connected to the computer at the time
(QKNl ) . The alarm occurs at PK during deferred address
cycles and at QK during operand cycles.
10-10 March I961
10-2.5.2 IN-OUT ALAEMS. (See Fig. 10-3- )
In-Out Selection Alarm (IOSAL) . The lOSAL flip-flop is set whenever
an lOS instruction is performed which tries to change the mode
(lOS 3XXXX) or select a new drive (lOS 6XXXX) of an In-Out mit
which is in the maintenance mode. The alarm occurs at PK of the
lOS instruction.
In-Out Miss Indication Alarm (MI SAL) . The MISAL flip-flop is set
by the IOCm'^^-'-^ level. The alarm indicates that some In-Qat unit
has missed a line of data.
10-2.5.3 OPERATION CODE ALAEM (OCSAL) . (See Fig. 10-3-) The OCSAL flip-flop is
set whenever the computer attempts to execute an instruction \-/ith an
undefined operation code. The alarm can occur if an instruction word
with an undefined OP code is read out of memory or if an AOP instruction
specifies an undefined OP code in bits N ^ _ . In the first case,
2.5CC
the alarm is generated at PIT" of the PK cycle in which the OP code is
interpreted, i.e., when Pip. (PIp indicates that no deferred address
cycles remain to be performed. ) In the second case, the alarm occurs
at the time the AK counter is started during the AOP, i.e., when the
content of AKIR_ is being intei^reted.
10-2. 5. Ij- MEMORY PARITY ALARMS. (See Fig. 10-^4-.)
M Parity Alarm (MPAL) . The MPAL flip-flop is set whenever the
parity check circmt in the M register indicates that the operand
word just read out of memory into M has an even parity.
The alarm is generated 1.2 microseconds after QK" (QK is the
latest time at which a strobe can occur during a QK cycle) and
hence occurs at varying QK states depending on the instruction
being executed. The ' — ♦MPAL logic determines the time at which
the parity is checked. Note that the alarm is not generated when
a QSAL is generated (i.e., when QKM^ ), nor when the V Memory
is used.
N Parity Alarm (NPAL) . An NPAL is generated whenever an instruction
word or deferred address word which has an incorrect parity is read
out of memory into the N register. This alarm is generated in a
manner similar to the MPAL discussed above. However, in this case
Pk always occurs 1.2 microseconds after PK . (PK is the
latest strobe time.)
March I961 10-11
F Parity Alana (FPAL) . An FPAL is generated whenever a word is
read out of the F Memory into the OKIE register that has an
incorrect parity. The parity check is made O.5 microseconds after
a word is strobed into QKIR^„. Only one readout occurs during a
normal FK cycle but foiir readouts occ-ur during a FLG. Note that
during SPF and SPG instructions, and when register 00 is selected,
the words readout are not used. In these cases the parity is not
checked.
X Parity Alarm (XPAL) . The XPAL flip-flop is set whenever the
parity check circuit in the X register indicates that the X Memory
word just read out of memory into the X register has an even parity.
The alarm is generated at PK -^ or CSk . This is never less than
0.8 microsecond after the word is strobed into the X register from
the X Memory. Note that, although a zero word is placed in the X
register whenever X Memory register 00 is selected, the parity of
the word is correct since XP is set.
10-2.5.5 MISCELLANEOUS ALAEMS (See Fig. IO-5.) All the previous alarms have
virtually identical design, except for the individual alarm condition
logic which distinguishes them. The following alarTus have few similar
features, although each has an alarm flip-flop and can stop the computer.
T Memory Selection Alarm (TSAL) . This alarm is designed to protect
the circuitry in the T Memory by turning off the read -write currents
whenever the TSAL alarm flip-flop is set. This occurs whenever a
voltage transition takes place on one of the memory address MAS
lines while the read -write currents are turned on. The TSAL flip-
flop can be cleared only by a ' ♦CE level. There is no
flashing indicator associated with this alarm and it cannot be
suppressed, but on the other hand the alarm does not stop the
computer .
Synch System Alarm (SYAL) . This alarm is generated whenever the
Synch System generates a SYNCH STOP pulse. This level sets both
the SYAL alarm flip-flop and a flashing indicator. The flip-flop
can be cleared only by pressing the CLEAR UNSUPPRESSED ALARMS push
button. This alarm stops the computer, but does it directly by
clearing the START^ flip-flop, rather than by starting the alarm
delay coimter ADK.
10-12 March I961
Mousetrap Alarm (Mousetrap) . This alarm is used to detect and
remember various malfunctions of the computer. Currently it
determines whether the S iMemory read-write flip-flops SR and SR
are cleared at a time when they should remain set during an S
Memory cycle. Such an event will generate a I — ♦MOUSETRAP level.
There is neither a flashing indicator nor a suppression switch
associated with the Mousetrap alarm. ¥hen the alarm is set it will
always stop the computer in the same way that a normal unsiippressed
alarm would. It is also cleared in the normal manner.
10-2. 5.6 ALARM LEVEL (AL) . (See Fig. 10-6.) Most of the alarm conditions which
stop the computer do so by generating the AL level. This level clears
the STARTp flip-flop in the start control system and starts the alarm
delay counter ADK. It will also clear the START flip-flop if the AUTO
START switch is not turned on^ so that the computer will not restart by
itself when ADK returns to ADJ
):^°.
The AL level is simply the OR of the MOUSETRAP alarm and all of the
following alarms which are not unsuppressed: PSAL, QSAL, MISAL^ lOSAL,
OCSAL, MPAL, EPAL, FPAL and XPAL. The AL level can be removed only by
clearing all the set alarm flip-flops which generate it. Note that SYAL
can also stop the computer^ but it doesn't use the AL level to do this.
10-2.5.7 CHIME CONTROL. Two different audible indications of an alarm condition
are generated using a two-tone chime. One tone indicates that a sup-
pressed alarm, i.e.;, one which does not stop the computer, has occurred.
The other tone indicates that an unsuppressed alarm, i.e., one which
stops the computer (at least momentarily), has occurred. Each of these
audible indications can be suppressed by switches on the console.
Chime on Suppressed Alarms . As shown on Fig. 10-7, this chime is
generated by the flashing indicators associated with the alarm flip-
flops. Only QSAL, PSAL, MSAL, lOSAL, OCSAL, MPAL, NPAL, FPAL and
XPAL can generate this indication, and then only when the Sijppress
Chime on Unsuppressed Alarm switch is turned off.
Chime on Unsuppressed Alarms. This chime is generated when either
the ADK counter has been started or when a SYAL has been generated.
In the first case the chime level lasts as long as ADK is in state
ADK , which is determined by ALD , whenever a MOUSETRAP or an
unsuppressed QSAL, PSAL, MISAL, lOSAL, OCSAL, MPAL, EPAL, FPAL or
XPAL occurs. In the second case the level is generated directly by
the flashing indicator associated with SYAL.
March I961 10-13
10-2.5-8 ALAEM DELAY COUNTER (ADK) . This counter is started whenever an Al alarm
level is generated. After it has started no other PK, QK or CSK cycle
can begin imtil it has returned to its resting state. The ptirpose of
the counter is to stop the computer, and then after the necessary
operations have been performed, to allov the computer to be started again
in a controlled manner. The co-unter uses variable delay units to slow
down its rate of counting to about 0.1 seconds per cycle.
The logic of the counter is illustrated in Fig. 10-8. The AL level sets
the first delay unit ALD . ADK_ is then set and the counter remains in
01
the ADK state until ALD clears itself synchronously with an CC pulse.
Drxring this time the CHIME ON IMSUPPRESSED ALARMS is sounded. Presumably
transient conditions, which might have caused the AL level, have by then
had a chance to disappear.
The counter next enters the ADK state by setting ADK^, and also sets
the second delay unit, ALD . While ALD is set the first delay unit
recovers. During this time the computer simulates the pressing of the
STARTOVER push button, if the PASOFA switch is on, and simulates the
PRESET button, if both the PASOFA and the AUTO START switches are on.
Note that in the latter case only the Control Element exclusive of the
start -stop control is preset.
When ALD clears itself the counter will wait in the ADK state until
the CLEAR UNSUPPRESSED ALARMS button is pressed unless the AUTO START
switch is on. The CA.^ flip-flop is set when this button is pressed.
When either CA.^ or the AUTO START switch is on, ADK can proceed to state
10
ADK wherein the unsuppressed alarms which generated the AL level are
cleared, and then to state ADK where it remains until AL is generated
again.
Note that CA^ and ADK together act as a synchronizer for CLEAR UNSUP-
PRESSED ALARMS nulses.
10-3 INTERLOCKS
10-3.1 GENERAL DESCRIPTION. The general function of the vajrious interlock flip-flops was
described in Chapter 6. This chapter will discuss the specific logic that sets and
clears these interlocks.
1.0 -ih March I961
In certain cases two or more interlocks will have a related f -unction. The times
at which these interlocks are set can overlap- To clarify the time relation of
the interlocks, figures will be given to show the relative times at which these
interlocks are set and cleared in terms of the basic counter cycles.
10-3.2 IKSTRUCTI05[ INTERLOCKS
10-3.2.1 INSTRUCTION INTERLOCIC (PI ) . This interlock determines whether a PK
instruction word or QK operand word memory cycle can occur.
The logic for setting and clearing PI is shown in Fig. 10-9- A graphic
1 -^
illustration of the duration of PI.^ is shown in Fig. 10-10.
PI is set if an instruction requires a QK cycle. It is then cleared
after the QK cycle starts, thereby indicating that the next instruction
(PK) or change of sequence (CSK) cycle can begin. (See also PI dis-
cussion.) PI is always set at essentially the same time d-uring a PK
cycle, but it is cleared at various times during the QK cycle that
follows. The specific time depends on the kind of operation being
performed. Thus PI provides additional timing information about when
the next PK or CSK cycle is permitted to start.
PI is set during instructions which require QK cycles either at the end
of the instruction word PK memory cycle or, if deferred address is
required, at the end of the PK ultimate cycle. The set pulse occurs at
if the computer can proceed with the execution of the instruction.
,^2a
WAIT 23CX
i.e., if the PI level exists, or PK" if the computer has been forced
to wait before the decision is made to continue.
PL is usually cleared as soon as the QK cycle begins, i.e., when QK is
in the Qk'^ state and the QI start level exists. However, any IX (AUX,
RSX, EXX, ADX, DPX or SKM) or W (SPF or SPG) operation code postpones
clearing PI until later during the QK cycle. For example, in the case
16a
of ADX, PI^ is not cleared until QK^ . In the case of SPF and SPG,
PKIR^p is protected from the effects of the next PK or CSK cycle until
the FK cycle is finished with it. In the case of SKM, N is protected.
1
In the remaining instructions PI helps protect the N input to the
1 2,1
X Adder until the XA output has been used. Note that although in some
cases PI is cleared twice during a QK cycle only the first of such
pulses has any affect on the interlock.
March I961 10-15
10-3-2.2 INSTRUCTION INTERLOCKg (PIg)- ^^2 ^^ ^^^ during a PK instruction vord
memory cycle whenever deferred address cycles are required. It then
remains set, and serves to distingiaish subsequent PK cycles which are
associated with the deferred addresses. It is not cleared until the
ultimate deferred address cycle (the one which does not obtain a word
from memory) .
The logic that sets and clears PI is shomi in Fig. 10-11. Note that
the term CSK^''''^ ' SS ** is present only for reasons of wiring con-
venience and has no effect on the operation of the interlock. (See also
PI;- discussion.)
10-3. 2. 3 INSTRUCTION INTERLOCIC (PI ) • This interlock determines whether a PK
instruction word memory cycle or a CSK change sequence cycle is to occur
next. The logic that sets and clears PI is illustrated in Fig. 10-12.
PI_ must be set before a change sequence cycle can begin. It can be
cleared during normal operation only at CSK of a CSK cycle.
On the other hand, there are three kinds of occasions at which PI can
be set:
1) One of these times is simply at CSIi ' during a change of
sequence cycle. A change of sequence always takes place to
the highest priority sequence -which wants attention and usuaJ -ly
no flags can be set during the CSK cycle. Thus the SS
level usually exists at CSK when the CSK cycle is ending.
However, if the sequence meta bit on the program counter of the
new sequence is set, and the Trapping Sequence is trapping on
such bits (see Chapter 15), then the flag of the Trapping
njj ■RTTQ QTCC
Sequence will be raised and SS might exist at CSK
In this case PI_ is set and the change of sequence is followed
by another change of sequence, this time the change of sequence
is to the Trapping Sequence.
2) The second class of timing covers the situations when PK is in
a waiting state and the delay synchronizer counter DSK is
rimning. In these cases DSK will stop when interlock conditions
determine either that PK can continue from where it was stopped
when DSK started or that PK must go to PK (if it is not already
there) and a change of sequence cycle should start. There are
three such situations:
10-16 March I961
a) PK can already be In PK -while DSK is coimting if an
instruction dismissed the current sequence at a time
■when no sequence wanted attention. In this case DSK
,^ ATT KEQv
cycles -until some sequence -wants attention (^SS )
at CSK^"^^. At that time^ PI is set and a change of
sequence occurs next. Two special situations must be
taken into account. One situation is that if the
highest priority sequence -which -wants attention is
sequence zero (KD ) then the change of sequence will
always occur, even tho-ugh the computer is already in
sequence zero. This means that sequence zero -will,
once it has been dismissed, start up again at the TSP
address when its flag is raised again. The other sit-
uation is that if the highest priority sequence which
wants attention is the c-urrent sequence (iv ), then,
with the above exception about sequence zero, PI^ will
not be set since no CSK cycle is required.
02
b) PK can be waiting in PK while DSK is counting if the
Arithmetic Element is busy when PK attempts to obtain
an instruction or deferred address word from it. In
this case PI„ will be set if the PI level
. ^ ^ oc^lC^ T.xAE CH SEQ . ,. , .,,
exists at CSK . PI indicates, as we -will
shortly see, that a higher priority sequence wants
attention and the last instruction executed did not
"hold".
c) PK can be waiting in PK while DSK is counting if
either a TSD instruction tries to use an In-Out unit
which is not ready (IOCm ) or because an instruction
tries to use the Arithmetic Element while it is busy
LV SEQ
(AEI). In either case, PI will be set if the PI ^
level exists.
3) The third class of time covers the situations when PK is
counting and a change of sequence condition occurs.
One of these conditions can occur at the end of the PK
memory cycle at PK and covers the same situations which
are covered at PK!"^ above and again involve the PI
level-
March I961 10-1?
The others occiir either at PIC or PK of instructions
which do not hold or which dismiss. If a sequence which
has its flag up can generate the PI level, then PI
is set and the PK cycle of the instruction is followed by
a CSK change of sequence cycle.
10-3.2.i<- INSTRUCTION INTERLOCK (PI. ) • PI. simply remembers the hold value of
the last instruction executed. The logic that sets and clears PIi is
shown in Fig. 10 -l4.
Since the decision to execute an instruction is indicated at the earliest
by the decision for PK to advance to state PIv , this is also the earliest
time at which the PI, flip-flop can be changed. Whatever hold value is
then placed in PI, is held until the next time a decision is made to
execute an instruction.
The PI, interlock is used in the interlock level logic to decide whether
the SS level can contribute to sequence change decisions.
10-3.2.5 INSTRUCTION INTERLOCIC (PI ) . PI is similar to PI^ in that it is set
during a PK instruction word cycle whenever deferred address cycles are
reqmred. The logic for setting and clearing PI^ is shown in Fig. 10-1^4-.
5
However, there are two kinds of deferred address cycles: (l) the deferred
address cycles which require memory words, and (2) the ultimate deferred
address cycle which does not require a memory word.
Pip and PI serve to distinguish the three kinds of PK cycles, as shown
in Fig. 10-15.
Initially both Pip and PI are zero during the instruction word cycle.
If the instruction word requires a deferred address, i.e., NT , then
PI is set at Pk and PI at VYT . Both interlocks remain set during
subsequent deferred address memory cycles -until finally a deferred address
word is obtained in which N . At Pk during this cycle, PI^. is
cleared. The next PK cycle is then identified as the "ultimate" cycle,
since the Pip and PI interlock condition exists at the beginning of the
cycle. PKA. (see Chapter ll) then remains cleared throughout this PK
cycle so that no memory is selected and no memory word is read out.
During the first part of the ultimate PK cycle the svm of the base address
and the selected index register in the last deferred address is placed in
N^ ^ . The index bits from the original instruction word are retrieved
from QKIR„„ and placed in N„ ^ „ . .
OJ? 3. b - 3.1
10-18 lykrch 1961
Tlie logic performed in the -ultimate cycle after PI is cleared at PIT"
is, aside from memory logic, identical to the logic which would have been
performed after PK in the initial instruction word memory cycle if no
deferred addresses were required. This can be seen by examining the logic
performed in PK" through PIC ; nearly all of the logic will be seen
to contain a factor of Pip-
After the ultimate cycle, PK continues on with the execution of the
instruction using the final effective base address.
IO-3.3 ARITHMETIC ELEMENT INTERLOCKS. Registers in the Arithmetic Element can be used
either as Memory Element flip-flop storage registers or as storage registers for
the intermediate and final results of arithmetic computations. The instructions
involved in this second case can be divided into two classes: (l) the simple load
and store type instructions, and (2) the more complex add and shift type instructions.
OPR AK
The more complex instructions generate either the PKER AE or QKER levels (see
Chapter ik) , and make use of a variety of Arithmetic Element interlocks.
10-3.3.1 ARITHMETIC ELEMENT BUSY INTERLOCK LEVEL (AEB) . This interlock level
simply indicates whether or not the Arithmetic Element control counter
00 /-
AK is in its AK resting state. This is showQ in Fig. 10-16. When the
AEB level exists, i.e., AK is in its PJC resting state, then it is
permissible for immediate use to be made of the flip-flop registers in
the Arithmetic Element.
Note that AEB is an interlock control level and not an interlock flip-
flop. It is discussed here instead of Section 10-^ only for convenience
in grouping together the Arithmetic Element interlock conditions.
IO-3.3.2 ARITHMETIC ELEMENT PREDICT INTERLOCK FLIP-FLOP (AEP) . The AEP flip-flop
optimizes the speed of the Arithmetic Element instructions by predicting
when the current use of the Arithmetic Element will end. The logic
setting and clearing this flip-flop is shown in Fig. 10-17-
The interlock is set whenever an instruction which might use both the AK
and ASK coimters starts to make use of the Arithmetic Element. This occurs
at FK in all AOP instructions and at Qk" in all other instructions
which use both AK and ASK.
The interlock is then cleared at some time during the AK cycle of these
instructions. This time is at most 2.8 microsecond before the end of the
AK cycle, i.e., at most 2.8 microseconds before the AEB level occurs.
March I961 IO-I9
10-3' 3- 3 ARITHMETIC EIEMENT INTERLOCK LEVEL (AEI). This interlock level is
discussed here, rather than later to keep it in the context of the two
other Arithmetic Element interlocks. AEI is generated by the logic
shown on Fig. IO-I6. During AOP instructions, AEI is simply equal to
AEP J but during QKIR instructions it starts with QIT ^ earlier then
IO-3.3.I1 ARITHMETIC ELEMENT INTERLOCK DURATIONS. The duration of the Arithmetic
AE
Element interlock levels during QKIR instructions is illustrated in
Fig. 10-18. Since AEP is needed only to help generate AEI, it will be
ignored in the following discussions.
AEI is used in the various PK decision states of a subsequent instruction
in order to help determine whether or not the PK cycle shoirLd continue.
The PK cycle of a subsequent instruction can begin as early as 0.4 micro-
AK
seconds after the QK cycle of a QKIR instruction begins. The earliest
(320!
PK decision state occurs at PK . Hence the AEI level must be generated
earlier then the QK time at which AEP is set. For this reason, the
AEI level is started, as indicated by the logic, with QK . Also, the
logic of the PK decision states is designed with a bias towards continuing
the PK cycles, rather then towards causing a change of sequence. For this
reason the AEI level ends when AEP is cleared, before the AEB level occurs.
In all cases when the new instruction tries to make use of the Arithmetic
Element before the Arithmetic Element is actually free for a new use, the
AEB level is itself used in waiting state logic to hold up the new in-
struction. However, the AEB level itself is never used by a new PK cycle
until late enough in a new instruction so that it doesn't need to be
generated before QK" when AK is started.
The duration of the Arithmetic Element interlock levels during an AOP
Instruction is illustrated in Fig. IO-I9. In this case AEI is simply
equal to AEP . AEB and AEI are again used to influence the same PK
decisions just described. Here, thoiigh, the levels reflect a different
situation since AOP does not require a QK cycle and AK is started directly
by PK during the execution of the AOP instruction. Both the AEB and AEI
levels begin when AK is started. This is adequate for interlocking
purposes since no subsequent PK cycle can begin until after the current
PK cycle has ended, i.e., after the two levels have been generated. The
termination of the levels is the same as in the previous case, since the
levels end in a manner which is independent of whether the operation
being performed in the Arithmetic Element was originated by an AOP or an
ordinary OP code.
10-20 March I961
Note, however, that am AOP can call for an operation vhich does not
use ASK, nor even AK. This can occiir since the full six bits in
W ^ of the AOP specify the operation. Some of these, the
IIKXXX • ADD • SUB • DSA, are just like the corresponding QKTR
operations which use both AK and ASK. Others, ADD + SUB + DSA, use AK
but not ASK. In these, AEP is cleared as soon as AK starts, so that AEI
ends before the PK cycle ends. Finally, the IIXXXX codes are not defined
and do not actually use AK. Hence, neither AK or ASK is used and both
the interlock levels end before the PK cycle ends. In this last case,
however, an OCSAL alarm is also generated at the present time.
10-3.ij- MISCELLANEOUS IKTERLOCKS
10 -3. 4.1 E REGISTER BUSY IIOTERLOCK (EB). The EB interlock indicates when the E
register is busy during an operand cycle and can not yet be used for a
new purpose. The logic for setting and clearing EB is shown in Fig. 10-20.
EB is set whenever a QK operand cycle starts, since the E register is
used by all instructions which require an operand.
The interlock is then cleared as soon as the register is no longer needed
during the operand cycle. This occurs at QK during all store type
instructions which are not placing the operand in the V—^^ Memory. All
other instructions, except SPG, use the E register until QK , at which
time EB is cleared. SPG alone clears EB during a non-QK state. This
situation will be understood after it is discussed in Chapter 16.
EB need be set only diiring operand cycles, and not during other uses of
the E register, since conflicting demands for the use of the E register
can arise only when one of these demands already is an operand cycle use
of the E register.
10-3.4.2 Q REGISTER BUSY INTERLOCK (QB). The QB interlock indicates when the Q
register is busy during an operand cycle. The logic for setting and
clearing QB is shown in Fig. 10-21, and simply shows that QB is set when
a QB cycle begins, and is cleared when it ends. As in the case with EB,
if these are conflicting demands for Q, one of them always already
involves an operand cycle.
Note that QB also indicates whether the M register is busy, since nearly
3ICK
all QK cycles require the use of M until QK
The relative durations of EB and QB are graphically illustrated in
Fig. 10-22.
March I961 10-21
10-3.^^-3 F MEMORY IWTERLOCK (FI). Before any SF (FLF or FLG) or JA (JPA, JEA and
JOV) instructions can be executed, the F Memory interlock FI must be in
a cleared state. Fig. 10-23 shows the logic for setting and clearing
the FI interlock.
FI is cleared when a JA or SF type instruction is executed. This occurs
at Pk either during the instruction word memory cycle if no deferred
address cycles are required or during the ultimate deferred address cycle.
The FI flip-flop is set at FYT during an FLF or a JA type instruction.
TCC
During a FLG instruction, FI is set at FK .
The FI interlock permits the contents of the F Memory registers to be
obtained during the execution of these instructions earlier than they
would otherwise be.
Note that FI is set during FLF and FLG in such a manner that FI can
START
contribute to the QI level.
10-3. Ij-. 4 X REGISTER BUSY INTERLOCK (XB). The XB interlock serves two functions.
The first is to indicate that the X Memory is busy with a READ-WRITE
cycle. This is done by setting it whenever an X Memory READ cycle is
initiated, and then clearing it when the WRITE cycle is performed. Thus
XB is set whenever XR is set, and it is cleared during the XWK cycle.
(See Fig. IO-2J+.)
The second function of the interlock is to predict, by 1.6 microsecond
when the X Memory WRITE cycle will end. This prediction ability enables
a PK cycle to start that much time before the WRITE cycle ends. Thus,
XB is cleared at XWIT , 1.6 microsecond before XW is cleared at XWIC .
10-3-^.5 X WRITE REGISTER INTERLOCK (XW) . This flip-flop is described more
throughly in Chapter 12 in the section on the X Memory. XW is used as
an interlock to indicate when an X Memory WRITE cycle has ended. The
flip-flop is set at XWK to turn on the X Memory write current and is
cleared at XWIT . (See Fig. 10-25.)
10 -ij- INTERLOCK CONTROL LEVELS
10-4.1 INTRODUCTION. The general function of the various interlock levels was described
in Chapter 6. This section will examine their function in greater detail by
examining the logic that generates these interlock control levels.
10-22 March 1961
10-i4-.2 PK, QK AND CSK INTERLOCK START LEVELS. The following interlock start levels
determine when instruction word, deferred address word, operand word and change of
sequence counter cycles can begin. These are the basic counter cycles in the
computer and are the only such start levels which are influenced by the console
stop-start controls. The logic that generates these interlock start levels is
shown on Fig. 10-26.
START
10-ij-.2.1 INSTRUCTION MEMORY CYCLE INTERLOCK START LEVEL (PI l). The logic
governing the start of a PK instruction word memory cycle depends on the
PI 1 level. The fact that such a PK cycle is req.uired is indicated
by the fact that PI^-
The logic first of all requires that the stop-start system permit such
a cycle. This is indicated by START^ • PKS^ ' AL. Also, there must be
neither a CSK nor a DSK cycle required, i.e., the PI • CSK^ condition
must be satisfied. The QK operand cycle, if one is required by the
previous instruction, must have already started and progressed to the
point where PI is cleared. Also, any previous \ise of the X Memory (or
X Adder) must be aLnost over (XB ) . Finally, the memory overlap conditions
must be settled. The memory selected by P from which the instruction
will be obtained must not be the same memory used by the previous QK
— 5~S V v"
operand cycle, i.e., the (P Q + • • • + P • Q^) condition must be
satisfied and the Wo Overlap switch must be off (NO ) . If these overlap
conditions are not satisfied the previous QK cycle must be over (QB ).
qrri/vprn
The PI 1 level is used by PK when it attempts to start an instruction
word memory cycle, and also by the Memory Address Selector in order to
turn on the selected memory (see Chapter 11 ) .
START
lO-i^.2.2 DEFERRED ADDRESS MEMORY CYCLE INTERLOCK START LEVEL (PI 2). The
logic governing the start of a PK deferred address word memory cycle
START
depends on the PI 2 level. The fact that such a PK cycle is required
is indicated by the fact that PI .
The stop-start control must permit such a cycle, i.e., the STARTp • PKBp
condition must be satisfied. The XWK cycle initiated by the previous PK
cycle must be almost finished (XB ), and the Q register must be available
(QB°).
START
The PI 2 level is used both to start PK and to turn on the selected
memory in all the intermediate deferred address cycles. However, during
the "ultimate" cycle it is used only to start PK. In this case only the
stop-start control conditions are really relevant as start conditions.
Note that PI„ during all intermediate cycles and that PI^- during the
ultimate cycle.
Iferch 1961 10-23
START
10-i^-.2.3 OPERAND MEMORY CYCLE IMTERLOCK START LEVEL (QI ) . The logic governing
the start of a QK operand word memory cycle depends on the QI level.
The stop-start control must permit such a cycle, i.e., the STARTT • QKS
-) '-
condition must be satisfied. A QK cycle must be required (PI, ), and, in
-'- ■]
the case of SPF and SPG, the FK counter cycle must be aliaost over (FI ) .
START
The QI level is used both to start QK and to turn on the selected
memory.
START
\Q)-\.2..\ CHANGE OF SEQUENCE CYCLE INTERLOCK START LEVEL (CSI ). The logic
governing the start of a CSK change of sequence cycle depends on the
__,^START , ^
CSI level.
The stop-start control must permit such a cycle, i.e., the STARTp • CSKS
condition must be satisfied. Any QK cycle required by a previous in-
struction must have already started (PI-,), and PK must be in its PIT
resting state. Also, since CSK makes immediate use of the X Memory and
the E register, these must both be available, i.e., the X¥ • XB and EB
conditions must be satisfied, respectively.
START
The CSI level is used only in the starting of CSK when a change of
sequence cycle is required.
10-i|-.3 SEQUENCE CHANGE INTERLOCK LEVELS. These interlock levels are used in the "decision"
states of PK (see Chapter 9)^ ^^^ also in the DSK cycles, to determine whether the
computer should continue executing instructions in the current sequence, or change
to a new sequence.
The logic generating these sequence change interlock levels is shown on Fig. 10-27 .
10-4.3.1 CHANGE SEQUENCE INTERLOCK LEVEL (PI^^ ^■^'^) . Towards the end of the PK
cycle of each instruction executed the decision miist be made whether to
execute the next instruction in the current sequence. A change of sequence
is made usually when either the current instruction does not hold (PKER )
and some other sequence of higher priority wants attention (SS ),
"DTS RFO
or when the current instruction dismisses (PKIR^^ • PKIR ) and any
ATT REO ^
other sequence wants attention (SS ) . The Sequence Selector levels
can also indicate other reasons for changing sequences, as described
earlier and in Chapter 12.
10-2ij- March I961
10-ij-.3.2 ARITHMETIC ELByiENT CHMGE SEQUENCE INTERLOCK LEVEL (PI ^) . If
the computer attempts to obtain an instruction, deferred address or
operand "word from an Arithmetic Element flip-flop register and the
Arithmetic Element is perfonning a QKER type instruction, indicated
by the AEI level, then the computer is forced to "wait and perhaps to
make a change of sequence.
ATT nxT Q*f?Q
The PI level reflects the conditions for changing sequence. If
the last instruction executed did not hold (PIl ) and some higher priority
nil ■R'C'Q
sequence "wants attention (SS ) "while the Arithmetic Element is busy
(AEI), then the level is generated.
10-ij-.3.3 LEAVE SEQUENCE INTERLOCK LEVEL (PI''^^ ^^'°^) . The PI^ ^^ ^'^'^ level alone
is used in the PK decision state. In the PK ' decision state a more
complex situation exists for determining "whether to change sequences.
Here the change "will occur if, "when the PI level exists, the
computer is attempting to execute an instruction which requires the
AE
Arithmetic Element (PKIR ) or obtains an operand from the Arithmetic
OK" AE
Element (PKIR • XA ) . The change will also occ"ur if the computer is
attempting to execute a TSD and either the selected 10 "uait is not
available (IOCm ) or the QK cycle of a previous TSD is not finished
(QKIR • QB ) when some other sequence wants attention (SS ) .
.WAIT
10-lf.3.1^- INTERLOCK WAIT LEVEL (PI ). The computer can arrive in the P
^22/23
decision state and be unable to change sequence (PI ) and also be
"Unable to continue to execute the instruction. This latter condition is
WAIT
indicated by the PI level. In fact, the instruction cannot be executed
WAIT
unless the PI level exists.
It can be seen that PI is simalar to PI except for the absence
of the Sequence Selector flag information (see Fig. 10-27). PI
simply indicates that the computer is attempting to perform an instruction
which can not be done at the moment and that no sequence change condition
exists either.
lO-ij-.i; MISCELLANEOUS COUNTER START INTERLOCK LEVELS. The FK, XWK, AK, ASK and D3K counters
are slaved to the PK, QK and CSK counters in the sense that their start conditions
are usually generated at partic-olar times during PK, QK and CSK cycles and last for
only 0.4 microseconds. Hence, these counters "osually must be in their resting states
and must start immediately when the start conditions are generated. FK is the only
one of these counters that "uses an interlock flip-flop In its start level and even
then only in a restricted class of start situations.
March I961 10-25
None of the start conditions for these co\xnters directly reflect the console stop-
start controls.
ADK was discussed earlier in the chapter in Sect. 10-2. 5. 8.
I cm AID (Tl
^^_^.-,.^ , ..^.xv...x ^^^.,^^. ^^.^.^ ^^.^^ , -^FK). The logic governing the
START
FK level logic is shown on Fig. 10-28.
Normally FK is started when the QK cycle starts during the execution of
instructions which use the F Memory in order to obtain a configuration
word. The two instructions which specify configurations (SPF and SPG)
do not start FK until QK after the new configurations have been placed
in the E register. The Arithmetic Element jump instructions (PKIR )
SF
and the instructions which file configurations (PKIR ) start FK by
clearing the FI interlock in PK and waiting for EB to be cleared. In
these cases, FK then starts as soon as it returns to FK . Note that the
QK cycles of FIF and FLG wait in QIC until FI is set. Similarly, the
PKEI cycles of JOV, JPA and JTJA wait in FK^ until FI is set.
qrpA'prn
10-lj-.lj-.2 X MEMORY WRITE COUNTER START LEVEL ( ' ►XWK) . The XWK counter is
started only when a word is to be written in the X Memory. The logic
for starting the coimter is shown in Fig. IO-29.
The co'onter is always started at PK" in a deferred address cycle (PIp),
and in the same state diaring instructions which do not make special use
of the X Memory (PKIR ) dixring a PKEI cycle. These PKEI instructions
310;
all start XWK at PK , unless execution of the instruction is abandoned
, ^^2/23 ^ ^^LV SEQ
at PK ' because a PI
level occurs.
During the QK cycle of QK instructions which change the contents of an
X Memory register, XWK is started as soon as the new word is placed in
the X register. This occurs at QK for RSX and EXX and at QK^ for
AUX. Note that in all these instructions XWK goes through an earlier
cycle started at PK" . This extra earlier cycle is performed so that
the X Memory register read out during the PK cycle is not left in the
cleared state in case the stop -start or alarm controls inhibit the QK
cycle of the instruction. When the QK cycle does occur the X register
is cleared out again at QK in preparation for the QK XWK cycle.
XWK is also started in change of sequence cycles at C3K in order to
store the old program counter in the X Memory.
10-26 Iferch 1961
10-lj-.lj-.3 AEITHMETIC ELEMENT COUWTER START LEVEL (^-^ ► AK) . The logic for
this level is shown in Fig. 10-30. AK is started at PK during AOP
1 ha AK"
and at QKT" for all QKIR instructions.
lO-lj-,4.1^ ARITHMETIC ELEMENT STEP COUNTER START LEVEL (ASK] + 1 ►ASK). The
logic for this level is shown in Fig. 10-30. This counter counts only
during QKER instructions. It does not coimt in the usual manner
(every 0.^ microseconds) since it co'onts once each time AK goes through
A'POV"
a subcycle during QKIR instructions. It starts from the state it
PRESET
was preset to by the ASK condition, and advances to state zero
by this ASK count level.
I START
10-1|.1^.5 DELAY SYNCHRONIZATION COUN-IER START LEVEL (I — » . DSK) . The delay
synchronization co-onter is started only when the computer cannot continue
executing instructions in the current sequence and no change sequence
condition exists. In these situations the DSK counter is started in
order to synchronize signals arriving in the Sequence Selector from the
In-Out Element.
CSK, can be set in any of the "decision" states of PK, but PK must be in
one of the associated waiting states before DSK can start counting. These
02a 230; ooa
waiting states are PKT , FKT and PKT . XWK must also be in state
zero when DSK starts counting.
The logic generating the DSK start level is shown on Fig. 10-31-
10-5 COUNTERS
10-5.1 GENERAL DESCRIPTION. The general function of the various counters was discussed
in Chapter 6. In this section, the function of each counter will be discussed in
greater detail. The actual count logic for each counter will also be discussed.
The dynamic interlocking of the counters is discussed in Chapter 9-
10-5.2 INSTRUCTION COUNTER (PK) . The count logic for the PK counter is of two types.
One type is used during the memory cycle when an instruction or deferred address
word is obtained from memory. This is the part of the PK cycle which extends from
PK to PK!"^ . The second type of count logic is used in PK ' and in the addi-
tional PK states (PKEl) used in the execution of special instructions. The memory
PK count logic is shown on Fig. 10-32 and the special instruction PK count logic
is shown on Fig. 10-33-
March I961 10-27
Basically, one of three types of action can occur d\iring the PK cycle:
1) PK can count into the next state.
2) PK can skip to some "preset" state.
3) PK can "wait" in a state lontil a decision to go on can be made.
The PK memory cycle carries the PK counter from PK , when the appropriate start
condition is satisfied, through to PK . Skips occur from states 01, 02 or 06 to
state 09, and from states 15 or l6 to 22, depending upon the memory selected.
During the "ultimate" deferred address cycle (PKA. ) a similar sort of cycle occurs
except that no memory is selected. The starting condition used when PK is in state
zero depends upon whether an instruction cycle (PI^) or a deferred address cycle
(PIp) is to occur.
020;
Only one decision state occurs during a PK memory cycle. This is at PK during
a V_-, cycle where the AEI level is examined if the selected register is in the
Arithmetic Element.
When PK finishes the instruction and all the deferred address cycles by arriving
22CX
at PK with Pip another decision must be made about whether to execute the
WATT T V *TPO
instruction. At this time, the PI and PI levels are examined. P K can-
2h WAIT
not advance to PK and actually go on to execute the instruction until the PI
exists.
»k2^
Once PK reaches state PK the computer is committed to executing the new instruction.
DIS
This usually does not involve further use of PK. All PKIR instructions send PK
DIS
back to state zero from state 2k, and start a QK cycle. The PKIR instructions
send PK through a PKEI cycle from state 25 through to state 31, and start a QK
cycle only if they require an operand from memory.
DIS
Some of the PKIR instructions can make PK wait in state 25 if certain interlock
conditions are not satisfied. The interlock involved is usually EB, but can also
be QK, AEB or EI.
10-5.3 OPERAND COUMER (QK) . The count logic for the QK counter, like that of the PK
counter, is of two types. One type is used during the memory cycle while an operand
word is obtained from memory. The second type of count logic reflects the special
timing required by the execution logic of certain instructions. Unlike the PK
count logic, the two QK types of count logic overlap, i.e., the type that reflects
the instruction requirements usually occurs in the middle of the memory cycle and,
in part, at the same time as some of the memory count logic.
The memory count logic is shown on Fig. 10-3^ and the instruction cotint logic is
shown on Fig. 10-35-
10-28 March I90I
The QK counter can skip and jump states^ and wait in states, as in the case of the
PK counter. Hovever, there are no "decision" states in QK, and waiting can occur
^ 03
only in QK .
The memory count logic is primarily a function of which memory is selected. QK
qrpAjjrn qq to
waits in state zero until the QI level is generated. From QK to QK the
succession of states is determined entirely by the memory selected. The counter
then enters the instruction section. The memory section of the QK cycle does not
21 2.1 31
occur until QK • From QK to QK the count logic is again determined by the
memory selected, except that QKIR^ type instructions can cause QK to skip states
22 and 23.
The only waiting state in QK, other than Qiv , is QK when the operand is located
in the V_,.„ Memory. QK will wait in QK , if an Arithmetic Element register is
J:'!'
selected, until the AE3 level indicates that the Arithmetic Element is available
for use.
A j"ump to QK from QK takes place if the operand is in the V Memory, since no
parity check is required. (QK^ ' is used primarily to allow time for the parity
check circuits to stabilize.)
The instruction section of the QK cycle does not depend on the memory selected but
rather on the particular instruction (or class of instructions) being executed.
(See Fig. IO-35.) The instructions involved are: TSD, INS, SKM, ST-, LD-, FLF,
FLG and COM. Each of these instructions requires QK to go through a different
sequence of states in the instruction section of the QK cycle.
10-5.^ CHANGE SEQUENCE COUNTER (CSK) . The change of sequence counter actually functions
as two counters, as described in Chapter 6. One of these is the change of sequence
counter which uses states zero through seven. This counter is usually referred to
as the CSK counter. The other counter is the delay synchronization counter which
uses states 8 through 11. This counter is referred to as the DSK coimter even
oSq; J.1CC
though the states are labelled CSK through CSK . This point of view can be
better understood, as illustrated in Fig. IO-36, by considering CSK as a three
stage counter and CSK as an interlock flip-flop. The logic controlling the counter
is shown in Fig. 10-37-
START
¥hen CSK. , the counter can perform a change of sequence cycle when the CSI
level occurs and CSK is in state CSK . Since the CSI " level inhibits the
counter only when CSK is in its CSK resting state, the counter, when started,
will run through to state CSK and then back to state CSK without interruption.
Note that the essential interlock condition in CSI for a change of sequence
cycle is PI^.
March I961 10-29
CSK, is never set unless DSK is to perform a delay synchronization cycle. In this
case the count logic does not permit DSK to count, once CSK, is set, until XWK is
in state zero and PK is in state 02, 23 or 00. The count logic again inhibits the
JLlCt
count -when CSK is cleared in CSK , since the CSK count circuit on CSK inhibits
the carry from CSK-, to CSK, vhen CSKT so that the next state of CSK is CSIT .
Hence, if CSK, remains set in CSK^ , DSK counts from CSK^ to CSIT , and if
iia J-lct OOa
CSK, is cleared in CSK then DSK counts from CSK^ to CSK
CSK, is set in any of the PK decision states vhen the computer is unable to decide
whether to continue executing the instruction or to make a change of sequence.
In PK this occurs when the computer is attempting to obtain an instruction from
an Arithmetic Element flip-flop register and the AEI level is present. At least
one DSK cycle is performed before the PI " level is examined.
220; WAIT LV SEQ
In PK , CSK, is set when the PI level is present and the PI level is
not. PK then enters PK^ where DSK cycles occur. CSK, can not be cleared until
^^ ITWAlf „^LV SEQ -
either the Pi or PI level occurs.
DTS PEQ
Instruction which dismiss (PKIR • PKIR ) cause CSK, to be set during the
3ia
PKEI cycle if no other sequence wants attention. This occurs at PK" for most
of these instructions. However, it occurs at PK"^ for JPX and JKX because the
DTS RFO 25Ct
PKIR level does not exist after PK during these instructions. DSK then
ooo;
begins to cycle when PK reaches PK and CSK, is then cleared when some sequence
+ ++ ^. /'oqATT REQ.
wants attention (SS ).
Note that CSK, is cleared and the interlock condition examined only when DSK is in
J.1Q!
state CSK . Note also that when another DSK cycle is to follow the level
■ ♦CSK, is used to generate 10 clock pulses.
10-5.5 X MEMORY WRITE COUIWER (XWK) . The | ^^■^'^ ►XWK level causes the XWK counter to
start counting by setting XWKL^ , as shown in Fig. IO-38. The counter will then
continue to count through to XWK and then back to XWK .
While XWK is counting the X Memory parity compute circuit first stablizes and then
the X Memory write current is turned on and off via XW.
10-5.6 F MEMORY COUNTER (FK) . The FK counter logic is shown on Fig. 10-39- The FK
1 START
counter will start counting, when the I ^ FK level occurs, if it is in its
FK resting state and the FK8 flip-flop is cleared.
10-30 March I961
If the counter is not executing a FF type instruction (SPG or FLG), the coimter
will cause, one complete F Memory read-vrite cycle while it is counting through to
02a ooa
state FK and then back to FKT
When either a SPG or FLG instruction is performed, FK counts from Fiv through to
FK and through one extra state, in which FKS • FIT . In the process FK
executes four complete read -write cycles.
As shown in Fig. 10-i|0, FK is only a 9 state counter even though it has four stages.
The special FKS flip-flop of the counter is set when the computer reaches state
FiC^ , and then is cleared on the next cc pulse while the other stages remain
cleared.
10-5.7 ALARt4 DELAY COUNTER (ADK) . See Sec 10-2-5.8 for a discussion of this co'onter.
10-5.8 ARITHMETIC ELEMEKT COUNTER (AK) . AK differs from all the other control counters
in that it is actually a shift register and the flip-flops of the counter are used
030;
directly to generate the AK control time levels. Thus AK is in state AK when
AIT" . The logic for the counter is shown in Fig. 10-^1.
Ct. J
ooa
AK is placed in state AKT , before it is started, whenever an operation code is
placed in AKTR. This also occurs whenever a preset level or a Synch System AE
Stop condition is generated, or whenever an undefined AKTR operation code occurs
(AKTR ) .
The counter is also cleared at the end of the various AK instruction cycles. For
ADD, SUB and MUL this occurs at AK^^, for DIV at AK^"*^, and for DSA at M^'^^ .
For TLY it occurs in AIT when ASK has reached state zero (ASiC • ASIC) . For NOA,
Ota '
NOB and NAB it occurs in AK when ASK reaches state zero in the case where the
number being normalized is zero. If the number being normalized is not zero or if
a SH type instruction (SCA, SCB, SAB, CYA, CYB or CAB) is being performed, a dif-
ferent clearing logic is used. In all these NOR and SH type instruction the clear
p'olse occurs in AIT , but in the case of the NOR type instruction only when all
the numbers being normalized are actually normalized and in the case of the SH type
only when all the coimts in D are finished.
Ogo; I START
AK starts counting from AET when the ' — ^- AK level occurs. It then continues
to count until either a skip or waiting state is reached or the counter returns to
JDOa
AKT^ and there is no Synch System AE Stop condition. During NOR and SH type in-
struction AK simply counts through to All where it remains until AK is cleared
as described above. During DSA, AK counts through to AK"^ (and then returns to
OOa o "^a
AK ) . In the case of ADD, SUB or MUL, AK counts until it reaches either AIT"'
OQQ! oory C\0a Cs'^a
or AK . These instructions return AK to AK from AK , but the AK situation
varies and will be covered below.
March I961 10-31
DIV and TLY are more complex. Both, of them stop the AK count ptLLses when AK is in
states mP^^, AK°^°, A]P^ or AKt'""'"", or when ASK^ • ASK^, or when AK is in state
08q; and ASIC- Note that AK is not cleared until AK reaches Ak during a DIV,
020;
but that during a TLY AK is cleared at AET . Hence in the latter case none of
the logic in AK states later than AK apply.
As will be seen in Chapter l6, AK can jump forwards or backwards in ADD, SUB, MUL
^.^ ^^ . . ^..^^ ^^^..^ ^^^j^^..o -- --.^-.-- ^.. --.-- ' ►AK logic. Note that this
preset logic never places AK in state
AK^°«.
In the case of ADD and SUB, AK jumps from AIT to either state AK or AIT
depending on the length of the subword in the Arithmetic Element. The amount of
time allowed for carries to propagate in the carry circuits is controlled in this
manner .
During a MUL, AK waits in AIT until ASKl, while the multiplication is performed,
and then jumps to Aii or Aa to do the final carry.
During a DIV, AK jumps ahead to AK or AK"^ in order to enter the subcycle in
which the divide steps are performed. This subcycle extends from AEv or AK
through to Ak . After the subcycle is first entered, AK jumps back to AK or
AK^ from AK^^ until ASk£ • ASK^ ' ASK? in AeP . AK then jumps ahead out of
loa ' DSa , iia
the subcycle to AKT from AKT^ (and continues on to AKT^ before returning to
ooa,
AK ).
10-5.9 ARITHMETTIC ELEMENT STEP COUNTER (ASK) . ASK is used to control the number of times
a subcycle in AK is repeated during most of the QKIR and AOP instructions.
The ASK counter logic is shown in Fig. 10-^2.
ASK is cleared when the ' ^ ^'~ ^ ^K level occurs. It is then preset to some
oia
negative number at AK . This value is dependent on the length of the longest
active subword in the Arithmetic Element and on whether the instruction uses single
(AKTR^) or double (AKIR^^) length subwords.
An ASK count pulse is generated whenever AK performs a subcycle. These subcycles
can be only one AK state long so that AK simply waits until the ASK count is
"complete". Usually this completion of the ASK count occurs when ASK goes positive,
i.e., when ASKL becomes a zero. During some instructions, however, ASK can end
with a positive number as large as two.
During NOR and SH type instructions, ASK coimts while AK waits in AK"^ . Note
that the content of ASK does not influence the n-umber of AK subcycle repetitions
during SH type instructions.
10-32 March I961
During MUL, ASK counts once in APT , and then counts each time AK goes through
the subcycle in Ak . Thus, the suicycle is repeated one less time than the
length of the subvord.
2a
During TLY, ASK counts each time AK goes through the subcycle in Ak
During DIV, ASK counts each time AK goes through the subcycle which passes through
Afv . Note that this subcycle actually begins in AK or AIT and goes through
08a
to AK .
March I961 10-33
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CHAPTER 11
MEMORY ELEMEm'
TABLE OF CONTEKTS
11-1 INTRODUCTION
11-2 MEMORY ADDRESS SELECTOR
11-3 STROBE SELECTOR
11-ij- INHIBIT SELECTOR
11-5 S MEMORY
11-5.1 ADDRESS DECODING
.2 READ-WRITE OPERATION
11-5
11-6 T MEMORY
11-6
11-6
11-7 V MEMORY DECODING
11-7
11-7
11-7
11-7
11-7
11-7
'11-8 PARITY
1 ADDRESS DECODING
2 READ-WRITE OPERATION
1 PLUGBOARD STORAGES A AND B
2 TOGGLE SWITCH STORAGE
3 SHAFT ENCODER
k REAL TIME CLOCK
5 INPUT MIXER
V^_ MEMORY
LIST OF FIGURES
11-1 MEMORY ELEMENT BLOCK DIAGRAM
11-2 TYPICAL MEMORY ADDRESS SELECTOR DIGIT STAGE
11-3 INSTRUCTION MEMORY ADDRESS SELECTOR CONTROL LEVEL
ll-i+ PKA MEMORY SELECTOR CONTROL FLIP-FLOP
11-5 DFA MEMORY SELECTOR CONTROL FLIP-FLOP
11-6 OPERAND AND DEFERRED ADDRESS MEMORY ADDRESS SELECTOR CONTROL LEVEL
11-7 QKA MEMORY SELECTOR CONTROL FLIP-FLOP
11-8 INSTRUCTION AND DEFERRED ADDRESS, READ-WRITE, STROBE AND INHIBIT SELECTOR LEVEL CONTROL
11-9 OPERAND, READ-WRITE, STROBE AND INHIBIT SELECTOR LEVEL CONTROL
11-10 MEMORY STROBE INTO M AM) N REGISTERS FOR S, T, U AND V=^ MEMORIES
11-11 MEMORY CLEAR AMD STROBE INTO N REGISTER
11-12 MEMORY CLEAR AND STROBE INTO M REGISTER
11-13 TYPICAL MEMORY DIGIT INHIBIT LOGIC STAGE
11-11+ s, T AND U xMEMORY INHIBIT SELECTOR CONTROL FOR INSTRUCTION WORD REWRITE
11-15 S, T AND U MEMORY INHIBIT SELECTOR CONTROL FOR OPERAND WORD REWRITE
11-16 S MEMORY ADDRESS DECODER, READ-WRITE UNIT AMD STACK INHIBIT SELECTOR
11-17 READ-WRITE UNITS OF S MEMORY
11-18 S MEMORY READ-WRITE SR FLIP-FLOP CONTROL LOGIC
11-19 S MEMORY READ-WRITE SR FLIP-FLOP CONTROL LOGIC
March 19 6l
11-1
11-20 S MEMORY INHIBIT FLIP-FLOP COIWZROL LOGIC
11-21 T MEMORY 1ST AND 2ND LEVEL X AND Y ADDRESS DECODERS
11-22 READ-WRITE UNIT OF T MEMORY
11-23 T MEMORY READ FLIP-FLOP CONTROL LOGIC
11-2^4- T MEMORY WRITE FLIP-FLOP CONTROL LOGIC
11-25 T MEMORY INHIBIT FLIP-FLOP CONTROL LOGIC
11-26 V MEMORY DECODER
11-27 PLUGBOARD STORAGE A
11-28 PLUGBOARD STORAGE B
11-29 TOGGLE SWITCH STORAGE
11-30 SHAFT ENCODER
11-31 REAL TIME CLOCK
11-32 TYPICAL STAGE OF V MEMORY INPUT MIXER
11-33 V^_ MEMORY INSTRUCTION AND DEFERRED ADDRESS WORD TRANSFER
FF
11-31+ v__ MEMORY OPERAND WORD TRANSFER
11-35 TYPICAL PARITY STAGE
11-36 M PARITY COUNT WITH S, T AND U MEMORIES
11-37 N PARITY COUNT WITH S, T AND U MEMORIES
11-38 X MEMORY PARITY COUNT
11-2 March 1961
CHAPTER 11
MEMORY ELEMEMP
11-1 IIWRODUCTION
The primary fimction of the Memory Element is to store program.s and data while they are not
being used.
The Memory Element consists of four separate memories. Three of these are magnetic core
memories (S, T and U) . The fourth^ or V Memory, is divided into two groups: a static
memory called ¥==■ (or V ) which can be altered manioally only; and a flip-flop memory
FF T
called V__ which can be altered by the machine. The V==- Memory consists of several
FF I'-c
different devices: plugboards, toggle switch registers, a shaft encoder and a real time
clock. The V__ Memory consists of the A, B, C and D registers in the Arithmetic Element
FF
and the E register in the Exchange Element. The general structure of these memories was
discussed in Chapter h.
There are several units in the Memory Element, each designed to control some aspect of the
over-all memory cycle. The more important of these units are shown in Fig. 11-1. Since
there is more than one memory in the Memory Element, it is necessary to have a unit that
determines which memory is selected and when. Both of these questions are answered by the
Memory Address Selector. There is also the problem of determining which register in the
selected memory is selected- This is determined by the address decoder associated with
each memory. The S, T and U memories each have read-write units that control the READ and
WRITE processes in these memories. A Memory Strobe Selector is used to read out the content
of the selected register and similarly a Memory Inhibit Selector is used to write information
into the selected register. Finally, there are two parity check circuits: one on the N
Memory buffer register and the other on the M Memory buffer register.
11-2 MEMORY ADDRESS SELECTOR
The function of the Memory Address Selector is to select the proper memory during an
instruction, deferred address, or operand memory cycle. The Memory Address Selector is
made up of the Memory Address Digit Selector and the Memory Address Control. The leftmost
bits in the P and Q registers are used by the Memory Address Control; while the remaining
bits in the P and Q registers are used by the Memory Address Digit Selector.
The Memory Address Digit Selector is made up of l6 similar stages. The i.jth stage is
associated with the i.jth bits in the P and Q registers. A typical stage is shown in
Fig. 11-2. The output levels (MAS) of each stage of the selector are routed to the address
decoders of the memories. There are usually four outputs from each stage, one for each of
the four memories, S, T, U and V. The exception is that not all l6 bits in the P and Q
registers are used by each memory. The S Memory uses l6 bits; the T and U memories each
use 12 bits; and the V Memory uses only 7 bits.
March 1961 11-3
There are two sitijations which generate MAS levels. The first sit\iation occijrs during an
instruction memory address cycle, when the contents of the P register are combined in the
SCT U or V)
Memory Address Digit Selector with a PM ^ ' level to generate a set of MAS levels.
STt U or V)
The PM ^ ' levels are generated by the logic shown on Fig. 11-3 • This logic
involves the state of the PKA and DFA interlocks and the state of the leftmost bits in the
P register. PKA must be set to ONE. This occurs at the start of either an instruction
cycle or an intermediate deferred address cycle. (See Fig. 11-if.) DFA must be cleared to
N 1
ZEEO. This occurs at the start of an instruction cycle. (See Fig. 11-5' ) PKA and DFA
then allow a PM ^ ' ^ level to be generated.
The second situation arises diiring an operand address cycle or during a deferred address
S(T U or V)
cycle. Either kind of cycle will generate QM ^ ' levels. These levels are then
combined in the Memory Address Digit Selector with the content of the Q register to generate
SCt U or V)
a set of MAS levels. The QM ^ ' levels are generated by the logic shown on
Fig. 11-6. This logic involves the state of the QKA, PKA and DFA interlocks and the state
of the leftmost bits in the Q register. If an operand cycle is executed, QKA is set to
OKE at the start of the operand cycle. (See Fig. 11-70 QKA is one of the interlock
SfT U or V)
conditions that allows a QM ' level to be generated. Only the different states
of the QKA, PKA and DFA interlocks distinguish between an operand address and a deferred
address. In a deferred address, both the PKA and DFA interlocks are set to OKE. The PKA
interlock is set when either starting an instruction cycle or executing an intermediate
deferred address cycle (see Fig. 11-ij-) . The DFA interlock is set to OKE when a deferred
address cycle is executed (see Fig. 11-5) • PKA and DFA is another interlock condition
that allows a QMi ' level to be generated.
Another set of levels, PKM ^ ' and QKM ' are formed in a manner similar
to the PM ^ ' and QHyT ' levels. The former levels control the function
of the read-write, strobe and inhibit selectors during the execution of an instruction,
operand or deferred address cycle. Generally speaking, these levels control the occurrence
of events during the operation of the specified memories by the indicated control counter.
g
E.g., PKM is used to control events during an S Memory read-write cycle that uses the PK
counter (this would be either an Instruction or deferred address cycle), and QKM is used
to control events during an S Memory read-write cycle that uses the QK counter (this would
be an operand cycle) .
SCT U or v)
The logic that generates the PKM ■" levels is shown in Fig. 11-8. There are two
situations which generate these levels. The first situation occurs in an instruction cycle
and requires that PKA be set to OKE and DFA be cleared to ZERO. In this case, the content
of the P register is used to select the proper memory. The second situation occurs in a
deferred address cycle and requires that both PKA and DFA be set to OKE. In this case the
contents of the Q register are used to select the proper memory.
S(T U or V)
The logic that generates the QKM ^ ' levels is shown in Fig. 11-9- The logic
requires that QKA be set to OKE. The contents of the Q register are used to select the
proper register.
ll-ij- March 1961
The QKM level (and similarly the PKM level) used for the V Memory is further divided into
V
levels for the V„„ and V== memories. The V__ Memory level QKM FF is formed by AlOing the
I'll ^J? ni^ y_
VMD level and the QKM level. The V==r memory level QKM FF is formed by AEDing the MD^^
level and the QKM level.
11-3 STROBE SELECTOR
The Memory Strobe Selector determines whether information coming out of the selected Memory
should be strobed into the M or N registers. The selected register depends upon whether an
instruction^ operand, or deferred address cycle is being executed. Fig. 11-1 shows the
information flow paths involving the computer and the Memory Strobe Selector.
The Memory Strobe Selector is basically a double gating circuit. A typical stage for one
memory is shown in Fig. 11-10. Four such gating circuits are used, one for each memory.
The first gate routes the information coming from the memory sense amplifiers to the M and
N p'ulse gate inputs. Which specific strobe pulse then occurs depends on the memory selected
and whether an instruction, deferred address, or operand cycle is being executed.
During instruction or deferred address cycles, a memory strobe pulse routes information
from the selected memory into the W register. The logic governing the memory strobe pulses
is shown in Fig. 11-11. The pulse which transfers OEES usually consists of two pulses, one
for each pair of quarters. The pulse which transfers ZEROES occurs in the third quarter
only. The first, second and fourth quarters of the N register are usually cleared at PKT^
For the S Memory, the strobe pulses occur at PKT^ during the READ cycle of the instruction
S 1 1 QI
or deferred address cycle (i.e., when the PKM level exists). They occur at PKT^ for the
T, U and V memories.
During an operand cycle, the operand strobe pulse routes information from the selected
memory into the M register. The logic governing the memory strobe pulse is shown in
Fig. 11-12. The pulse which transfers OIIES usually consists of two pulses, one for each
pair of quarters. The whole M register is usually cleared at QK'^ . For the S Memory,
the strobe pulses occur at Qk" d-uring the READ cycle of the operand cycle. For the T,
U and V memories, these pulses occur at PKT^ during the READ cycle.
The timing of other pulses during both PK and QK cycles assumes, if there is any question,
that the last memory strobe pulse will occur in the UP state of both counters.
Note that the Strobe Selector does not influence memory read-outs from the V^^, Memory since
r r
there are no strobe pulses per se when this memory is selected.
ll-i| INHIBIT SELECTOR
The Inhibit Selector is used to route inhibit currents to the memory cores in the selected
memory. A read-out from core memories is destructive, i.e., all the bits in the selected
March 19 6l 11-5
memory register are left cleared by the reading process. During the WRITE part of a read-
write cycle, inhibit currents are generated in the cores in which ZEROES are to be written.
The inhibit currents prevent the core from changing state during the writing process. As
we shall see, the Inhibit Selector effectively routes information from the buffer register
to the selected memory register in order that these inhibit currents can be generated in
the selected cores.
The Inhibit Selector consists of 38 similar stages (one for each bit). A typical stage is
shown in Fig. 11-13- There are three possible output levels in each stage, one for each of
the three memories, S, T and U. The V==- Memory does not require a WRITE cycle, thus no
inhibit logic is necessary. The corresponding fourth position in the Inhibit Selector is
used for non-memory purposes.
There are two situations in which the Inhibit Selector generates S(T or u) . . IWH levels.
The first situation occurs during the execution of an instruction or deferred address cycle,
when the contents of the W register are written back into the selected memory register.
The inputs to the Inhibit Selector in this case are the N. . levels, representing the
contents of the W register, and the N. . O SM. . levels.
The N. . OSM. . levels are generated by the logic shown on Fig. 11-lij-. The inputs in
this logic are the PKM levels (see Fig. 11-8) and levels from the SINE flip-flops. Note
that the SIM. . levels shown on Fig. 11-13 are completely different from the SINIi levels
shown on Fig. ll-l^J-. As we have seen, the latter are used in generating the former.
Similar logic generates the TINH. . and UIKH. . levels, using the W. . OTM. . and
W. . OUM. . level, respectively. Delay lines are used in generating the N OSM
levels only, since the S Memory requires that the N OSM levels vary sequentially
(i.e., "ripple"). The delay line is designed so that the level for each successive bit is
turned on after a delay step of O.OI5 microsecond.
The second situation occurs during the execution of an operand cycle when the contents of
the M register are written back into the selected memory register. In this case, the
inputs to the memory digit inhibit selector (Fig. II-I3) are the M. . levels representing
the contents of the M register and the M. . OSM. . levels.
The M. . OSM. . levels are generated by the logic shown on Fig. II-I5. The inputs in
this logic are QKM levels (see Fig. 11-9) and levels from the SIKIl flip-flops. The logic
generating the M. . OSM. . levels is very similar to that generating the N. . OSM. .
I'J -*-'J I'J i'J
levels .
11-5 S MEMORY
11-5.1 ADDRESS DECODING. The MAS lines from the memory address decoder are channelled
into four decoders and associated read-write units where they produce four sets of
10 decoder lines (YU, YV, XU and XV) . Each set of decoder lines contains eight
11-6 March I961
lines decoded from three MAS lines. E\^ery fotirth MAS line is associated with
either an SR?"^ or SR level. These levels are the inputs to the read-write uni
This unit generates the remaining two lines in each set of 10.
Bits MAS o and MAS^ ^ are also decoded in the memory stack inhibit selector into
l.o 1. [
four selection lines. These four selection lines are amplified and split into
four outputs per selection line. This gives a total of sixteen inhibit selection
lines.
II-5.2 READ-'WRITE OPERATION. The read-write units produce levels used by the current
regulators in the XU, XV^ YU and YV switch core drivers. (See Fig. ^-10^ Chapter k.)
These levels are generated by combining MAS levels and the SR and SR flip-flop
levels as shown in Fig. 11-17-
The S Memory read and write flip-flops^ SR and SR^ determine when the READ or
WRITE operation should take place. The P.EAD operation takes place when both flip-
flops are set to ONES. The WRITE operation takes place when both flip-flops are
cleared to ZEROES.
The logic for setting and clearing SR and SR is shown in Figs. II-I8 and II-I9
respectively. Although the piilse setting SR is generated at PIv or QIC , the
pulse doesn't actually get to the flip-flop until after the delays shown in Figs.
11-18 and 11-19.
The logic for setting and clearing the SIM flip-flop is shown in Fig. 11-20.
11-6 T MEMORY
11-6.1 ADDRESS DECODING. The MAS lines from the memory address selector are channelled
into four first level decoders as shown in Fig. 11-21. Each set of three MAS lines
is decoded into eight lines. The pair of eight decoder lines generated from the
MAS lines from 1.1 to 1.6 become the inputs to a second level decoder that in ti
generates 6k X selection levels. 6k- Y selection levels are generated in a similar
manner from the MAS
the T Memory itself.
MAS lines from 1.1 to 1.6 become the inputs to a second level decoder that in turn
manner from the MAS lines from I.7 to 2.3. The X and Y levels select the core in
11-6.2 READ-WRITE OPERATION. Actually each second level decoder has three inputs: two
coordinate selection levels and a read-write level. (See Fig. 11-21.) All three
levels must be present before an output level is generated.
Fig. 11-22 shows the read-write unit which generates the read-write level. Note
that this unit contains two read-write generators for each of the X and Y coordinates.
The inputs to this unit are the TR and TW^ levels and the 1.2 and 1.8 bits of the
T Memory address selector. If a READ operation is occurring, TR is set to ONE and
March I961 11-7
if a WRITE operation is occurring, TW is set to ONE. Note that the MAS and
MAS n lines are used redimdantly, i.e., they are inputs to both the first level
decoders and the read-write unit. This is done so that the second level decoder
can be split in half and each half driven by one read -write generator. This scheme
uses the selection logic to reduce the load on each read -write generator.
The logic that sets and clears TR is shown in Fig. 11-23. A T Memory read pulse is
generated at PIT and Qk . After a time delay of 0.^ microsecond, the T Memory
read flip-flop is set by this pulse. The same pulse clears the flip-flop after a
delay of 1.6 microseconds.
The logic that sets and clears TW is shown in Fig. 11-2^. The delay logic is
similar to that for TR.
The logic that sets and clears TINH is shown in Fig. 11-25- It is identical to
that for TW except for the different time delays used.
11-7 V MEMORY ADDRESS DECODING
The V Memory decoder requires two levels of decoding to select the proper V Memory.
The first level decoder is shown in Fig. 11-25. It consists of two decoders. The first
decoder decodes bits MAS,^ . to MAS,„ - into eight lines plus MAS,„ ^ and MAS,„ ^. The
vJ-.i Vj..j vl.J VI. 3
second decoder decodes bits MAS,^ ,, to MAS,^ „ into sixteen lines plus WD.^. VMD^„ is a
VI . 4- VI . 7 FF FF
decoding of bits MAS to MAS only.
The second level decoder is actually an "AND" circuit which combines the outputs of each
of the two first level decoders in order to produce levels which will select the proper
memory or the proper register in the proper memory. The second level decoders for the
Real Time Clock and the Shaft Encoder are shown in Fig. 11-26. The second level decoders
for the other V memories are shown in the figures illustrating those memories.
11-7.1 PLUGBOARD STORAGES A AND B. Each plugboard contains 16 registers of 37 bits each.
The Plugboard Storage A register-selection is shown in Fig. 11-27. The registers
i6x
are divided into two groups of eight registers. VMD„_. selects registers through
1 7X rBA
7, while VMD selects register 10 through I7. The specific register within the
XXO XX7
group is selected by VMD through A'MD .
Pliigboard Storage B register-selection is shown in Fig. 11-28. It is similar to
that described above except th;
two groups of eight registers.
that described above except that VMD^^^ and ^/I-'ID^^^ levels are used to select the
rri-D Jr^rsjD
11-8 March I961
11-7-2 TOGGLE SWITCH STORAGE. The toggle switch storage contains 2k registers of 37 bits
each. The register selection logic is sho-wn on Fig. 11-29- The registers are
12X
divided into three groups of eight registers. YMD selects registers through
l^X i4x
7; VMD^_ selects registers 10 through 17; and AMD selects registers 20 through
XXO XX7
27- The specific register within the group is selected "by VMD through VMD .
Note that only registers 0-17 currently exist.
11-7.3 SHAFT ENCODER. The Shaft Encoder is a device which converts an analog input into
a digital electrical representation by means of a dual brush-disc device. The
output of each Shaft Encoder represents a 9 "bit binary number. Four Shaft Encoders
generate a 3^ bit number. A toggle switch is used for the meta-bit.
The output of the Shaft Encoder is selected by the VMD level as shown on Fig.
11-30.
11-7. H- REAL TIME CLOCK. The Real Time Clock is a 36 bit counter plus a meta-bit. The
output of the Real Time Clock is selected by the VMD r. level as shown on Fig. 11-31.
The counter is divided into four quarters. A carry occurs from one quarter to the
next with an end-around carry from the fourth quarter into the first quarter.
The inputs to the counter are a clear pulse, beta clock pulse, and 100 kilocycle
pulse.
The outputs of the counter are combined in an output mixer with the VMD r. level
from the V Memorv decoder to form ^6 VMD^_^ levels. The VMD^,, , ,„ level is set by
CK CK 4.10 "^
a toggle switch.
11 -7. 5 INPUT MIXER. The output levels of the various 7:^^ memories are routed throiigh a
central input mixer. The output of the mixer then commtinicates with the M and W
registers in the central computer in the same manner the Memory Element sense
amplifiers do. There is one input mixer stage for each bit, making a total of 38
such stages. A typical stage and its inputs are shown on Fig. II-32.
11-7.6 Vpp MEMORY. The Y^ Memory consists of the A, B, C and D registers in the Arithmetic
Element and the E register in the Exchange Element. Read-out from these memory
registers is non-destructive.
When an instruction or a deferred address word is read-out, the contents of the
selected register are transferred into the N register via the E register as shown
in Fig. 11-33- Similarly, when an operand word is read-out, the contents of the
selected register are transferred into the M register via the E register as shown
in Fig. ll-3il-.
March 1961 11-9
Dixring these transfers through, the E register, the original contents of the E
register are temporarily saved in the M register imtil they can be returned to the
E register.
The logic governing these transfers is found in the chapters on the elements in
which the transfers occur.
11-8 PARITY
The function of the Parity Count circuits is to check the validity of the read-outs from
the S, T and U memories. All the bits of the full memory word are checked by a parity
coimt circuit in the M or N register. This circuit is made by pyramiding stages of
Individual parity circuits. A typical stage in this pyramid is shown in Fig. 11-35- In
a typical pyramid there are l6 such circuits.
The six bits k-.6 to U.IO, and 2.10 are not in the pyramid. Instead they are tied in as
shown in Fig. II-36 (for the M Parity Count) .
Two outputs are generated by each parity check circuit. One is a "check parity level"
which determines the correctness of the parity of the entire word. This level is used to
generate an alarm when the parity is Incorrect. The other level is a "compute parity
level". This level determines the parity bit inhibit current when the word in the buffer
register is written back in memory. This level forces the parity of the word written in
memory to always be a correct parity.
The M and N parity circuits also contain elements which control the value of the bit
written in the 4.10 position, as specified by the Trapping Sequence. This bit is written
either as a ONE, or according to the contents of the 4.10 bit in the buffer register itself.
The logic is described in Chapter I5. The logic for IWHM, and INHN, is given below.
The output of the larger pyramid, along with the output of another pyramid covering bits
EVEN
k.6 to 4.10 and 2.10 provide the "check parity level" MP n • The "compute parity level",
FVEN •
MP „ , consists of the outputs of the larger pyramid and of another pyramid foirmed from
bits 4.6 to 4.9 and the INHM^ (or mJ^ ^^ • SMB • SM^) level.
The N Parity Count circuit, as shown in Fig. 11-37^ is similar to the M Parity circ-uit
shown in Fig. II-36 but with two incidental differences. The first difference is that the
bits of the N register are used Instead of the M register. The second difference is in the
"compute parity level", NP . The secondary pyramid is also formed by bits 4.6 to 4.9
and IWM, level, but here INHMj^ ^^ is (nJ 3_q) + (DFA"^ • SMB • SWD^) + (DFA° • SMB • SNI^)
11-10 March 1961
The X Memory parity circuit shown in Fig. 11-38 uses a smaller pyramid vith a base of 8
stages for the l6 bits of the X Memory vord. The output of this pyramid is pyramided with
the output of the stage vhose inputs are the 2.8 and 2-9 bits. The outputs of this final
pyramid are the "compute parity levels" 0^-^q and XP g) . These levels are then fed into
another parity stage with the outputs of the XP flip-flop to form the "check parity levels"
(^,7andXP^J).
March 1961 11-11
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CHAPTER 12
PROGRAM ELEMENT
TABLE OF COKTEOTTS
12-1 INTRODUCTION
12-2 PROGRAM ELEMENT REGISTER DRIVER LOGIC
12-2.1 GENERAL DESCRIPTION
12-2.2 N REGISTER REGISTER DRIVER LOGIC
12-2.2.1 MEMORY TRANSFERS INTO THE N REGISTER
12-2.2.2 CLEAR N REGISTER LOGIC
12-2.2.3 E REGISTER TRANSFERS INTO THE N REGISTER
12-2.3 P REGISTER REGISTER DRIVER LOGIC
12-2. i|- Q REGISTER REGISTER DRIVER LOGIC
12-2.5 K REGISTER REGISTER DRIVER LOGIC
12-2.6 X REGISTER REGISTER DRIVER LOGIC
12-2.6.1 X MEMORY TRANSFERS INTO THE X REGISTER
12-2.6.2 XPS FLIP-FLOP LOGIC
12-2.6.3 P REGISTER TRANSFERS INTO THE X REGISTER
12-2.6.4 X ADDER TRANSFERS INTO THE X REGISTER
12-2.6.5 CLEAR X REGISTER AND SET X PARITY FLIP-FLOP LOGIC
12-2.6.6 COMPLEMENT X REGISTER LOGIC
12-2.7 X ADDER SELECT FLIP-FLOP (XAS) LOGIC
12-2.8 X ADDER CARRY FLIP-FLOP (XAC) LOGIC
12-2.9 OP REGISTERS REGISTER DRIVER LOGIC
12-2.9.1 PKIRqp register DRIVER LOGIC
12-2.9.2 QKER REGISTER DRIVER LOGIC
12-2.9.3 AKTR^^ REGISTER DRIVER LOGIC
^ ~> OP
12-2.10 CF REGISTERS REGISTER DRIVER LOGIC
12-2.10.1 PKER^^ REGISTER DRIVER LOGIC
CF
12-2.10.2 QKER^^ REGISTER DRIVER LOGIC
12-2.10.3 AJCCR^^ REGISTER DRIVER LOGIC
■^ CF
12-3 X MEMORY SYSTEM
12-3.1 GENERAL DESCRIPTION
12-3.2 X MEMORY
12-3.2.1 X MEMORY READ LOGIC
12-3.2.2 X MEMORY WRITE LOGIC
12-3.3 X ADDER
-\2.-h F MEMORY SYSTEM
12-ij-.l GENERAL DESCRIPTION
12-1J-.2 F MEMORY
12-5 OPERATION DECODING PROCESS
12-5.1 GENERAL DESCRIPTION
12-5.2 OP REGISTERS AVAILABILITY FOR DECODING
12-5.3 OP REGISTERS 1ST AND 2NtD LEVEL DECODING
March I961 12-1
12-5 -ij- CLASS DECODERS
i2-5.ii-.i pkiRqp class levels
12-5. ij-. 2 QKTR CLASS LEVELS
i2-5.il. 3 AKER^^ CLASS LEVELS
y ^ OP
12-6 CONFIGURATION DECODING PROCESS
12-6.1 GENERAL DESCRIPTION
12-6.2 SUBWORD FORM
12-6.3 ACTIVITY
12-6. .3.1 EXTENDED ACTIVITY
12-6. li- PERMUTATION
12-6.4.1 PERMUTED ACTIVITY
12-6.5 SIGN EXTENSION
12-7 SEQUENCE SELECTION
12-7.1 GENERAL DESCRIPTION
12-7.2 PRIORITY PATCH PANEL
12-7.3 SEQUENCE SELECTOR
i2-7.il- FLAG REGISTER
12-7.5 K DECODER
12-7.6 J CODER
12-7.7 K^^ '^^ NET
12-7.8 K^'^ "^ NET
LIST OF FIGURES
12-1 DIAGRAM OF MEMORY STROBE INTO N REGISTER
12-2 MEMORY STROBE INTO N REGISTER
12-3 N REGISTER CLEARING PULSE
12-2+ E REGISTER TRANSFER INTO N REGISTER (3RD QUAKTER IS A JAM TRANSFER)
12-5 X ADDER TRANSFER INTO P REGISTER
12-6 X ADDER TRANSFER INTO Q REGISTER
12-7 W REGISTER TRANSFER INTO K REGISTER
12-8 X MEMORY TRANSFER INTO X BUFFER REGISTER
12-9 P REGISTER JAM INTO X BUFFER REGISTER
12-10 X ADDER REGISTER JAM INTO X BUFFER REGISTER
12-11 X PARITY FLIP-FLOP SET PULSE
X BUFFER REGISTER CLEAR PULSE
12-12 X BUFFER REGISTER COMPLEMENT PULSE
12-13 X ADDER SELECT FLIP-FLOP LOGIC
12-12+ X ADDER CARRY FLIP-FLOP LOGIC
12-15 N REGISTER TRANSFER INTO PKER REGISTER AND HOLD BIT
12-16 PKERqp register TRANSFER INTO QKIR REGISTER
12-17 N^ REGISTER AND QKIR^^ REGISTER TRANSFER INTO AiGR REGISTER
12-18 N REGISTER TRANSFER INTO PKIR^^ REGISTER PKER^-^ REGISTER PULSE LOGIC
Or Or
12-19 CF MEMORY INTO QKIR^^ REGISTER
CF
12-20 E^ REGISTER TRANSFER INTO QKER^^ REGISTER
-L CF
12-2 March I961
12-21 W REGISTER TRMSFER INTO QKIR^„ REGISTER
12-22 QKTR^T, REGISTER CLEARING PULSE
12-23 5f^ REGISTER AKD QKIR„_, REGISTER TRMSFER INTO AKIR„ REGISTER
12-24 X MEMORY REGISTER SELECTION
12-25 TYPICAL X MEMORY WRITE CIRCUIT STAGE (i,j BIT OF REGISTER 00 ILLUSTRATED)
12-26 TYPICAL X MEMORY READ CIRCUIT STAGE (i,y BIT OF REGISTER 00 ILLUSTRATED)
12-27 X MEMORY READ LOGIC
12-28 X MEMORY WRITE LOGIC
12-29 TYPICAL X MEMORY ADDER STAGES
12-30 DEFER BIT STAGE OF X MEMORY ADDER
12-31 CF MEMORY SYSTEM
12-32 CF MEMORY REGISTER SELECTION
12-33 TYPICAL CF MEMORY WRITE CIRCUIT STAGE
12-34 TYPICAL CF MEMORY READ CIRCUIT STAGE
12-35 OPERATION CODE BLOCK DIAGRAM
12-36 SIMULTANEOUS EXECUTION OF INSTRUCTIONS
12-37 PKTRqp CLASS DECODER LEVEL LOGIC
12-38 QKIR CLASS DECODER LEVEL LOGIC
12-39 CONFIGURATION BLOCK DIAGRAM
12-40 SUBWORD FORM
12-41 PARTIALLY ACTIVE SUBWORD (36 BIT SUBWORD WITH ONLY QUARTER 1 ACTIVE)
12-42 EXTENDED ACTIVITY WITH SECOND QUARTER ACTIVE
12-43 QKIR EXTENDED ACTIVITY LOGIC
12-44 QICrR EXTENDED ACTIVITY
12-45 PERMUTATION AS DEFINED BY QKIR
12-46 QKER PERMUTED ACTIVITY LOGIC
12-47 SIGN EXTENSION LOGIC AND NETS
12-48 SEQUENCE SELECTOR (FLAG LOGIC CMITTED)
12-49 SEQUENCE SELECTOR STAGE (H 7^ O) AND FLAG LOGIC
12-50 SEQUENCE SELECTOR STAGE (H = O) AND FLAG LOGIC
12-51 FLAG REGISTER LOGIC
March 1961 12-3
CHAPTER 12
PROGRAM ELEMEIW
12-1 INTRODUCTION
Two basic opei-ations are perfonaed in the Program Element. One operation is the determination
of the addresses of instructions , deferred addresses and operands^ and the subsequent inter-
pretation of the instruction and deferred address words after they appear in the N register.
The second operation is the change of sequence^ i.e., the change of program counter in the
P register, "when indicated by the Sequence Selector.
The results of interpreting an instruction are usually a set of static levels used by the
remainder of the computer. Since the Program Element can be interpreting as many as three
instructions at once, there can be that many sets of levels about instructions, as well as
another set generated about sequence selection.
This chapter begins by discussing the register pulse logic associated with each of the
registers in the Program Element. The X and F memory systems are then explained. Next,
the decoding process, by means of which the data transferred into the Program Element is
interpreted, is discussed. Finally the sequence selection process is examined.
12-2 PROGRAM ELEMENT REGISTER DRIVER LOGIC
12-2.1 GENERAL DESCRIPTION. The following registers or flip-flops in the Program Element
are controlled by register drivers: K, P, Q, N, PKIR, QKIR, AJCIR, X, X Adder carry
flip-flop (XAC), X Adder select flip-flop (XAS), and FLAG. The FLAG register is
discussed in Sect. 12-7.i(.. The X Adder (XA) is treated as a register even though
it does not contain any flip-flops and hence does not have any associated register
drivers. The fimctions of the Program Element registers and their paths of
communication with other registers in the computer were discussed in Chapter 2.
A block diagram of the Program Element was given in Fig. 2-k-. This section will
discuss the register driver and pulse gate control of each of these registers.
12-2.2 N REGISTER REGISTER DRIVER LOGIC. This logic controls the transfer of information
from the main memory sense amplifiers and from the E register into the N register.
12-2.2.1 MEMORY TRANSFERS INTO TEE N REGISTER. Fig. 12-1 illustrates how data is
transferred from the memory sense amplifiers into either the M or N
register. A word in memory may be an instruction, deferred address, or
an operand. If the word is an instruction or deferred address, it will
be transferred into the N register during a PK cycle by a memory strobe
pulse. This strobe pulse is formed from a PK time level and a memory
selection level. The memory strobe logic was discussed in Chapter 11,
but will be briefly reviewed.
12 -i+ March I961
The logic for ttie N register strobe pulse is shomi in Fig. 12-2. An
instruction or deferred address word is strobed out of the memory sense
JLIQ!
amplifiers at PKr" . In the case of the S Memory, the strobe pulse is
routed through a delay line. Thus even though the pulse is initiated at
PK^°^, it is not finished until PIT ^.
12-2.2.2 CLEAR N REGISTER LOGIC. (See Fig. 12-3.) The N register (with the
exception of the third quarter) is cleared at PK in preparation for
receiving a word from memory. The "clear" pulse is not fired unless the
selection address is legal (PKIa ) or unless this cycle is the final
deferred address cycle. At other times, only quarters 2 and 1 of the N
JX
register are cleared. For PKIR type instructions, the clear pulse is
fired at PIT when PK need no longer wait in PIT . For QKIR type
Instructions (AUX, RSX, SKX, EXX, ADX, DPX and SKM), the clear pulse is
fired at Qli . The clear piilse is also fired at CSIT d-uring a change
of sequence cycle.
The third quarter of the W register is never affected by the clear N
register pulses. All transfers into W_ are janmed. This is done in order
to reduce the amount of noise in the X Memory selection lines decoded
from the N_ ^ ^ -, bits.
3-D - 3-1
12-2.2.3 E REGISTER TRANSFERS INTO TEE N REGISTER. The register driver logic for
these transfers is shown in Fig. 12-U. During an instruction or deferred
address cycle using the V__ Memory, the contents of the E register are
2.1a
transferred into the W register at PKT . During the final deferred
address cycle, the final base address is copied from E into N. D-uring
various instructions which make use of the X Memory as an operand memory,
the contents of E_ ^ are transferred into Np , . These transfers occur
at QK^5« ^^ Q^ia/
12-2.3 P REGISTER REGISTER DRIVER LOGIC. Information can be transferred into the P register
only from the X Adder. In addition to this single transfer path, the P register
has a counter which can index the contents of the P register by one. Note that
count circuit does not alter the contents of P_ .
The contents of both qviarters of the X Adder (with the exception of XA ) are
jammed into the P register during jump type instructions or during a change of
sequence. The logic is shown in Fig. 12-5. For these transfers to occur, the
computer must be in either an AUTO START or AL (no alarm) condition.
March 19 6l 12-5
The XA — ^ — ► P piilse occurs in the following situations:
1) When PK need no longer wait in PK for EB and the index jump condition
is satisfied (Xj) .
2) During a JMP instruction at PK . (This logic has a redundant term due
to wiring considerations.)
3) Whenever the Arithmetic Element jump condition (AEJ) is satisfied at PK
k) At CSPT when a new program counter is placed in the P register.
XA is copied into P^ only in case k, I.e., diiring a change of sequence. This
is the only situation in which the Pp bit is altered, since the sequence meta-
bit must be remembered, with the program counter, when the latter is placed in P.
The indexing circuit on the P register is used to add one to the contents of the
P register each time an instruction is read out of memory and executed. This
indexing pulse occurs at PK . During skip type instructions (SKX, SKM and SED),
the contents of P are indexed a second time if the skip condition is satisfied.
12-2. U Q REGISTER REGISTER DRIVER LOGIC. This logic controls the transfer of information
from the X Adder into the Q register as shown in Fig. 12-6. Q can hold the address
of either a deferred address or an operand.
The content of the X Adder is jam transferred into the Q register at the beginning
START
of the QK operand cycle, i.e., when the QI interlock level is present and QK
^ X)0Q:
IS m QK . This jam transfer also takes place when a deferred address cycle
START 1
begins, i.e., when the PI 2 and PI_ interlock levels are present and PK is in
PK°°«.
12-2.5 K REGISTER REGISTER DRIVER LOGIC. This logic controls the jam transfer of information
from N g into ¥L ^ _ . The transfer occurs during a change of sequence
at CSK^-' as shown in Fig. 12-7.
12-2.6 X REGISTER REGISTER DRIVER LOGIC. The X register is the X Memory buffer register.
The register driver logic controls the transfer of information from the X Memory,
X Adder and P register into the X register. This logic also controls the set X
parity pulse, clear X pulse and complement X pulse.
12-2.6.1 X MEIViORY TRANSFERS IlflO THE X REGISTER. The content of an X Memory
register is jam-transferred into the X register during either of the two
situations shown on Fig. 12-8.
The first situation occurs at PK^-"^ during the read-out of the X Memory
register specified by the J bits of an instruction or deferred address
word. The second situation occurs during the read-out of a new program
counter in a change of sequence. In neither situation is the content of
the X Memory register actually placed in the X register if the 00 register
is specified.
12-6 March I961
If the selected X Memory register has the same address as the current
program counter (i-e., if the IT level is present), then XPS must
also be present if the memory read-out is to occur*.
12-2.6.2 XPS FLIP-FLOP LOGIC. This flip-flop inhibits the X Memory strobe pulse
into X when the register selected has the same address or the current
program counter, is not register 0, and this is the first reference to
this register since the last sequence change. In this case all the cores
of. the register are cleared and only "junk" (with a 50-50 chance of a
bad parity) would be strobed into X. If XPS , then a clear piolse is
substituted for the strobe pulse.
The flip-flop is set whenever a sequence change occurs, and is cleared
the first time thereafter that the program counter register is referenced
during a PK cycle (if ever). See Fig. 12-8.
12-2.6.3 P REGISTER TRMSFERS IMTO THE X REGISTER. The content of the P register
is jam-transferred into the X register in the two situations shown in
Fig. 12-9.
The first situation occurs at PK during the execution of a PKIR
instruction, when the content of the P register is placed in the X Memory.
However, the transfer will not take place unless either the toggle switch
producing the XPAL level is turned on or the XPAL flip-flop is cleared
(indicating that no X parity alarm condition exists)-.
The second situation occurs during a change of sequence at CSk . Again,
the transfer will not take place unless the XPAL condition is satisfied.
12-2. 6. ij- X AJDDER TRMSFERS IIWO THE X REGISTER. The content of the X Adder is
jam-transferred into the X register by the logic shown on Fig. 12-10.
The path through the X Adder is the only one by which data can be trans-
ferred to the X Memory from the Memory Element. The XPAL condition must
be satisfied before any of these transfers can take place. These transfers
occur only during SKX, JPX, JTMX, RSX, EXX and AUX instructions.
12-2.6.5 CLEAR X REGISTER AED SET X PARITY FLIP-FLOP LOGIC. The clear X register
pulse serves as a substitute for the X Memory strobe pulse. For this
reason, the clear pulse also sets the X parity flip-flop to a OWE. This
guarantees that the X register contains a number with the correct parity.
Note that the register driver logic shown on Fig. 12-11 is, aside from
the time level gating, the inverse of the strobe pulse logic shown on
Fig. 12-8. The clear pulse occurs if either X Memory register is
selected or if the register has the same address as the current program
counter (K^^ "^) and XPS"^.
Mai'ch 1961 12-7
ox x6
12-2.6.6 CCMPLEMENT X REGISTER LOGIC. Dioring a JPX instruction (PKIR^p • PKLR^p),
the X register is complemented twice; once at PK'' , if VI^, and again
at PK , if EB . These complement pulses are the only features which
distinguish JPX from JTK.
"L5a
During a SKX instruction, the X register is complemented at PKT , if
PI° and PKIR__ differs from PKIR^^ . The X register is then re complemented
2 ^^ o 1
either at PK^^°^ if PKErJ;^ , or at PK^"^°^ if PKIrJ;^ .
In both of the above cases, a pair of complement pulses are generated
which contribute to the computation of the desired result in the X
register. The Pip condition permits the first of the pair of complement
pulses to occur only in the PKM cycle just before the PKEI cycle of the
instructions.
12-2.7 X ADDER SELECT FLIP-FLOP (XAS) LOGIC. This logic is shown in Fig. 12-13. XAS
determines whether the output of the X Adder is the sum of N and X (when XAS ),
or is simply the contents of N (when XAS ).
The register driver is controlled only by the PRESET level from the Control Element.
The remainder of the logic is pulse gate logic.
XAS is set to ONE at PIT during PK cycles which call for an indexed base address.
This occurs during instruction cycles (when no deferred address cycle is called
for), or when the final deferred address cycle is reached (PKIR • Plg)^ or
during all intermediate deferred cycles (PI^-) ■ Otherwise XAS is left cleared to
^5
3t
increment can be added to the index register
ZERO. XAS is always set during JX type instructions at PK in order that the
X J-OQ;
During AUX, ADX and all QKIR type instructions, XAS is set at QK" . This pulse
is not always necessary, but g-uarantees that the X Adder generates the desired
output. XAS is cleared at Qa for RSX and EXX, since in these cases the sum is
not desired.
During a change of sequence cycle, XAS is set at CSK^ so that the X Adder output
is the program counter coming from the X Memory when any index register other than
number 00 is selected; and is simply W_ (which contains the value of TSP), if
register 00 is selected.
12-2.8 X ADDER CARRY FLIP-FLOP (XAC) LOGIC. The logic is shown in Fig. 12-lij-. After the
terms to be summed in the X Adder have been placed in X and W , setting XAC to
ONE will "clear" the carry circuit of the X Adder. The carry logic then insures
that the X Adder output will be the correct Olffi' s complement sum. The pulse gate
12-8 March 19 6l
logic covers the sitiiation when this is desired. The set pulse occurs at PK^
and PIT during a SKXj at '?yP during a JX type instruction; at QI^'^'^ for all
QKIR type instructions; and at QIC and QK"°'^ for AUX and ADX. In the case of
the last two instructions, the pulse initiated at Qk is required since the
contents of Ng ^ are not set up until after QK*^-^*^. XAC is also set at CSJ^-^*^.
XAC is automatically cleared Q.h microsecond after it is set.
While the sum of a base address in N and an index register in X is being formed
between PIT and PK , the X Adder carry circiiit is forced into a "set" condition.
This causes the sum of an l8 bit number and its l8 bit OltE's complement to be all
ZEROS, rather than all ONES, if this sum shoiold be formed. The computed address of
an operand, deferred address, or next instruction then becomes the first register
of the S Memory (address O), rather than the last register of the V Memory
(address 377 777 (octal)), when, for example, the base address is 000 004 and the
index is 777 773. The logic for obtaining this result simply uses the PK^^^ O.h
microsecond time level to set the X Adder carry circuit at the time that XAC would
ordinarily have been used to clear it.
It should also be noted that the W bit is presented as an input to the X Adder
only when no deferred address cycles are called for. When PI^, the input to the
X Adder from the N^ position is forced to appear as a ZERO.
12-2.9 OP REGISTIES REGISTER DRIVER LOGIC. The operation registers are PKIR , QJCTR
and AKTR^p. These registers are used during the process of interpreting an
operation code.
12-2.9.1 PHRqp register driver logic. This logic is shown on Fig. 12-15. The
contents of K^^ - 3 7 ^°^ hits) are jam-transferred into PKTR at PK^^°^.
Simultaneously the content of N, (hold bit) is transferred into PKTR .
^' y H
12-2.9.2 QKIRqp register driver logic. This logic is shown on Fig. 12-l6. The
content of PKIR^p is jam-traiasf erred into QKIR^p at QK^°°^ when the QI^^^^
interlock permits the QK counter to start.
12-2.9.3 AKIRqp REGISTER DRIVER LOGIC. This logic is shown on Fig. 12-17. There
are two paths over which information can be jammed into the AKTR
register. The first path is from the N register. During an AOP instruc-
tion, the six bits in N^ g _ g -[_ are jam-transferred into AKIR at PK^^^
(providing that AK is in AIT at this time). The second path is from
the QKIR„ register. The content of QKIR_^ is jam-transferred into AKTR^^
130; AK
at QK during QKER type instructions.
March I961 12-9
12-2.10 CF REGISTERS REGISTER DRIVER LOGIC. The configuration registers are PKIR^p, QKIRj^j,
and AKTR . These are registers used during the process of interpreting the CF
CF
bits in an instruction and the configuration word selected.
12-2.10.1 PKIR„-„ REGISTER DRIVER LOGIC. This logic is shown on Fig. 12-18. The
Cr
contents of the five CF bits Wj^ g _ i^^i^ s.re jam transferred into PKIR^p
at PK of the instruction word cycle.
A counting circioit is incorporated in the PKIR^^ register that allows
instructions which make use of more than one F Memory register to address
four successive F Memory registers. These instructions are SPG and FLG^
as indicated by the PKIR"^'^ class level ("FF" denotes "Four conFigurations")
The F Memory "master" pulse is generated when FK is in its resting state
(Flf"^ • FK8°) and the L ^^^"^ ^ pK level occurs. The master puLse occurs
thereafter at 0.8 microsecond intervals at FK , FK and FK (i.e.,
when Fk'^ • FK ^) if certain further conditions are satisfied. These
a.l pjp
further conditions are that the instruction is a SPG or FLG (PKIR j,
,^0DDs
and that either the correct check parity condition exists (FP-^q )> °^
register 00 is used (PKIR^°), or that the F parity alarms are suppressed
(FPAL ). This pulse is delayed 0.1 microsecond, and, if Fk (i.e.,
when FK^°^, FK or FK^) , is used to index PKIR^j,. The master pulse
is also used in other F Memory system logic (see below).
12-2.10.2 QKIR REGISTER DRIVER LOGIC. There are three paths over which infor-
CF
mation can be transferred into the QKIR^jp register. These paths are
from the F Memory, E register and N register.
The F Memory strobe pulse is generated (see Fig. 12-19) by delaying
the F Memory master pulse O.38 microsecond and gating it with
(PKIR^l^ ■ PKIR ), i.e., the strobe pulse is permitted only if register
00 is not used and the instruction is not a SPF or SPG. The pulse is
further sated by PKIR^-„ , so that account can be taken of the difference
CF^
in polarity of the memory sense amplifier signals from the two halves
of the F Memory (see 12-4.2). In every existing use, this strobe pulse
is really a OIJE s transfer, even though lo is wrii^uen as a jam orans^er.
This pulse becomes a jam transfer only when the (unused) Complement
Mode (FC ) of operation of the F Memory is used.
The path from the E register involves only E . This path is used
LF
during SPF and SPG instructions (PKIR ) as part of the route from the
Memory Element to the F Memory. (See Fig. 12-20.) The logic is
LF
identical to the memory strobe pulse logic except for the PKIR factor.
X2-10 March I961
Here, of covirse, the piolse gate logic involves E rather than the memory
sense amplifiers. Note that this pulse causes only a OEE's transfer.
Note also that the input to QKIRp_j, is from a compute parity circuit
1'
based upon E.
The third path is actually a pair of paths leading from the W register
into the QKIR„„ register. (See Fig. 12-21.) At PIC^ of the first
10
deferred address cycle (PIp * XAS ) the N g bits are stored in
QKIE^„ for use later in the final deferred address cycle. Also, the
^ nia
contents of N^ ^ _ „ are transferred into QKIR__ at QIC during
3-D - 3o 2-1
an SKM instruction. The pulse gate logic here subtracts one from the
value of the two CF bits. A permutation is then formed from the right
three bits of QMR (the rest of QKIR^_, is cleared) that allows SKM to
select the desired quarter of the operand word.
The clear pulse for QKIR^-rp is separated into two pulses. The first
pulse clears bits QKIR^^ , whereas the second pulse clears
^^P, 9-3
QKIR^^ . The logic for the two pulses is identical except for an
^^2,1
additional term in the Q,KIR_,_ logic. This term is shown separately
'^P, 9-3
in Fig. 12-22. The remaining logic is shown for both pulses together.
The extra term in the clear pulse for bits QKIR_,_ occurs when the
^^9-3
transfer of bits W, /- , tr into QKIR takes place during an SKM.
The first clear QKIR„_ situation occurs by delaying the F Memory master
pulse 0.1 microsecond and, in the case of PKIR type instructions
(SPF, SPG), clearing the QKIR_,_, register in anticipation of - the E^
CF Q 1
OEE's transfer. An additional term involving FC can be neglected since
the circuitry is wired as if the flip-flop FC does not exist.
The second clear QKER situation occurs by delaying the F Memory master
pulse 0.5 microsecond so that when register 00 is being read out
(PKIR„^) , a clear QKIR-^ pulse can substitute for a memory strobe pulse.
The third situation arises when QKIR^^ is cleared at Piv of the first
1 ^^
deferred address cycle (PIp • XAS ) in anticipation of the W-, /-
bits being placed in QKIR^_.
12-2.10.3 AKIR^p REGISTER DRIVER LOGIC. Information is transferred into AKIR
from both' the N and QKIR_-_, registers.
Or
March 1961 12-11
The contents of W^ ^ ^ ^ are jam-transferred into the AKIE register
at PK during an AOP instruction. The contents of QKIR-,-^ are jam-
1 ^a AK -^
transferred into AKIR at QK during QKIR type instructions.
Also^ under these same conditions^ the extended activity levels
EXT ACT
QKIR) are jaia-transf erred into AKIR
12-3 X MEMORY SYSTEM
12-3.1 GENERAL DESCRIPTION. The X Memory system consists of the X Memory, X buffer
register, register selector, sense amplifiers, digit drivers, read-write drivers
and J Decoder (JD) . The function and structure of the X Memory system was covered
in Chapters 2 and k.
The register selector, X Memory and read-write drivers are illustrated in Fig. 12-24.
The register selector uses the E ^ bit and the JD levels obtained by decoding
W to determine which register (X ) is selected in the X Memory. The read-
write drivers use the outputs of the X Read (XR) and the X Write (XW) flip-flops,
in conjunction with the state of the N ^ bit, to control when read or write
currents should occur.
12-3.2 X MEMORY. The X Memory is a 6h register, 19-bit word magnetic core memory with
two cores per bit. It is a one -dimensional selection memory with registers
selected by the outputs of a two-stage address decoder. Each register selector
wire (see Fig. 12-24) is connected to both the read and write drivers. The
direction and magnitude of the current in this wire depends on whether a READ or
WRITE cycle is occurring.
In order to Tinderstand the WRITE cycle, it is essential to realize that only one
of the two cores per bit may be in the "set" state at any one time. However, both
cores may be in a "cleared" state. Before a WRITE cycle is executed, both cores
must be "cleared". Fig. 12-25 illustrates the current flow during the WRITE cycle.
In any given digit column, the X register flip-flop (or the XP o level) feeds into
the digit drivers and determines the direction of the current flow in the digit
winding. When the write driver is turned on, the current in the register winding
Induces a field in one of the two digit cores of the selected register in the same
direction as the flux induced by the current in the digit winding. The core which
then switches to the "set" state remembers whether a ONE or a ZERO is written.
The other core does not switch to the "set" state since the flux induced in the
core by the current in the register winding is in opposition to that of the digit
winding. The parity digit position uses the output of the parity compute circuit
to determine the direction of current flow in the digit winding so that a word is
always written with the correct parity.
12-12 March 1961
During the READ cycle (see Fig. 12-26), a large current flows in the register
winding in a direction opposite to that that occurred during the WRITE cycle.
This read current is large enoiigh by itself to switch all the cores of the selected
register which are in the "set" state to the "cleared" state. In the given digit
column, the change in flux resulting from the switching of a "set" core induces
a cxsrvent, or really a voltage pulse, in a direction opposite to the one which
existed in the digit winding during the WRITE cycle. Thus, if the OHE core was
switched during the write operation, then a positive pulse will appear in the
figure at the lower right end of the digit winding. This piilse is fed through
the differential amplifier and appears as a negative gate level on one of the two
transistors whose emitters are pulsed by the XM — ^ — ► X strobe pulse. This strobe
p-ulse then can get through to hit the OKE side of the flip-flop. After the READ
cycle, all the cores in the selected register are left in the "cleared" state in
readiness for a new WRITE cycle.
Note that at all times a current is flowing in the digit winding in one direction
or the other. This current does not influence the state of either core in any bit
position unless a read or write current also exists in the digit winding. During
a WRITE cycle, the write current is large enough so that one core will switch, but
not both cores. During a READ cycle the read cxxrrent is large enough to switch
whichever core is "set" by swamping out the effect of the digit current. The read-
out signal itself is observed as a voltage pulse superimposed on the digit ci^rrent.
Also, since the register selector is directly connected to the N ^ bits,
3-D - 3-1
some register winding is always selected. In order to reduce the amount of noise
on these windings caused by selection and deselection, the content of the third
quarter of N is altered only when a new X Memory register is to be selected. Thus,
the logic for the third quarter of W is quite different from that for the other
quarters of N.
12-3.2.1 X MMORY READ LOGIC. The logic for the X Memory read flip-flop (XR) is
shown on Fig. 12-27- XR turns on the read current in the selected
register for 0.46 microsecond. It is set no sooner than 0.2 microsecond
after the N ^ bits are changed. It is turned on at PK^^a ^^^^
Ola -^ ~ -^
CSPT in order to actmlly read out the contents of the selected index
register. It is turned on at CSK^ ' , and at QK^^^ ^^^^^ ^^x, RSX and
EXX in order to clear the selected register before a word is written in
the register.
12-3.2.2 X MEMORY WRITE LOGIC. The logic for the X Memory write flip-flop (XW)
is shown in Fig. 12-28. The write c\n-rent is turned on for 1.6 micro-
seconds during XWK cycles.
March 1961 12-13
12-3-3 X ADDER. The X Adder performs an l8 bit OKE's complement full sum addition. All
carrys and partial additions are internal and do not require separate pulses.
The X Adder consists of l8 bits or stages. Alternating stages of the X Adder are
identical in construction although all stages have the same fiinction. The last
stage of the X Adder, stage 2.9, must take into account the special nature of the
defer bit whenever N is Interpreted as the defer bit. However, it assumes the
function of just another adder stage at all other times.
A typical pair of X Adder stages is shown in Fig. 12-29. Each stage contains:
1) One or two partial add circuits
2) A carry-out circuit
3) A carry-in circuit
h) Either a force-carry circuit or an enable (or kill-carry) circuit
5) A full sum circuit
6) A selector and driver circuit for the output
The stages which contain only one partial -add circuit also contain a force-carry
circuit.
The partial-add circuit forms the partial sum of the contents of Np and the
contents of the X register. The partial sum logic is:
PS. . = W° . • X^ . + K^ . • X° . (= W. . ^ X. . )
Each stage also generates a carry-out (CYO) which essentially forms the carry
input (CYl) to the next stage to the left. The carry logic for even numbered
stages (XA^^g^ 2.6, 2.k, 2.2, 1-9, 1-7. 1-5, 1-3, l-l'^ ^^•
CYO. . = x] . ■ -N^ . + CYl. . • (X. . / N. .)
i-d i-J I'J i-J i-j i-J
The carry logic for odd numbered stages (XA,
2.9, 2.7, 2.5, 2.3, 2.1, 1.8, 1.6, l.ll, 1.2^
CYO. . = (X^ . + F^ .) ■ fcYI. . + (X. . ^ N. .)1
The two forms for the CY''0 logic are necessary because eacn soage acos as an mveruer,
and alternate stages must use dual forms of the logic.
The carry-in circuit (CYl) consists of an amplifier and an inverter to provide both
polarities of the carry level. Since inversion of a level takes a significant
amount of time, the inverted carry level is used only when the delay will not have
a cumulative effect on the over-all carry time.
12 -1^4- March 19 61
In the odd-n-umbered stages, the carry-In circuit is tied to the enable, or kill-carry
circuit. The enable or kill-carry circuit turns off (kills) the carry circuit when
the XAC flip-flop is set. However, the XkC flip-flop clears itself 0.4 microsecond
after being set. (See Fig. 12-29.) When the XAC flip-flop is cleared, the carry-
in circuit is enabled to transmit carry information.
The full sum circuit takes the outputs of the partial -add and carry-in circuits
and completes the addition process. The full sum logic for even numbered stages
is:
SUM. . = CYI. . • (X. . / N. .) + CYI. . • (X. . / N. .)
The full sum logic for odd nimbered stages is:
SUM. . = fcYI. . + (X. . ^ W. .)! • r CYI. . + (X. . = N. .)1
The duality of the circuits as described by these two equations is occasioned by
the inversion which takes place in each stage of the carry circuit.
The 2.9 stage of the X Adder must take into account the defer bit character of the
N bit. (See Fig. 12-30.) The logic is identical to other similar stages in
~ — OXA_ _ and L^
2.9
the X Adder, except that the ^-^ — OXA and 1-^^^ — OXA levels are substituted
J. ^^ ^^
for Wp and IC qj respectively, in the adder inputs. If the N bit is a OKE
2-9 ^-9 no 22 ^^
during PK cycles between PK and PK , this stage of the adder should receive a
ZEEO in order for correct address modification to occur. At these times Pip is in
the OM; state and because of this the > OXA^ ^ input occurs. At other times,
^'^ I
Pip is in the ZERO state, and because of this either the I O^Ap or the
' OXAp input is generated, reflecting the value of W .
12-k F MEMORY SYSTEM
12-1J-.1 GEEERAL DESCRIPTION. The F Memory system consists of the F Memory, the QKIR
CF
le function and stru
of the F Memory system were covered in Chapters 2 and h.
and PKIR_,-rn registers, and the PKIR^^ address decoder. The function and structure
CF CF
As shown in Fig. 12-31, the value of the five CF bits in the N register is trans-
ferred into the PKIR_,„ register. The content of the PKIR^-„ register is used for
Q-p o CF ^
two purposes. Normally it is interpreted as an address in the F Memory. However
in certain instructions it has a special purpose, eg., it is used to increment
index (X Memory) registers during JX type instructions.
March I961 12-15
The PKIR__ register has an indexing circuit which indexes the register during
execution of SPG and FLG instructions .
The information read out of the F Memory is transferred into the QKTR^-, register.
The content of this register is decoded into activity, coupling and permutation
information. (See Sect. 12-6.)
12-i+.2 F MEMORY. The F Memory is a 32 register, 10 bit word magnetic film memory. It is
a one -dimensional memory array. Register selection is by a two stage selector whose
inputs are the PKIR_,^ bits.
Each word selection line is connected to a switch core selected by the decoder.
(See Fig. 12-32.) A switch core is turned "ON" when the FR flip-flop Is set. The
five PKIR^„ bits then select the decoded register. When the core is switched "ON"
a current Is Induced in the word selection line. When the core is turned off a
diode in the word selection line prevents an opposite current from flowing.
During a WRITE cycle, the content of the entire buffer including the parity bit Is
written back into the F Memory. The direction of the current in the digit winding
determines whether a ONE or ZERO is written (see Fig. 12-33). A ZERO is written
if the QJCER_,_ bit is ZERO. The TW flip-flop controls the current in the digit
Or
windings and permits a ONE to be written during the WRITE cycle when the QKIR^^
bit is a ONE.
While the digit current is flowing, a ONE or ZERO Is written only if the magnetic
film spot is pulsed by the flux from the word selection line. If the spot contains
a ZERO and a ONE is to be written, the digit winding produces a flux in the opposite
direction to that existing in the magnetic film spot. However, the film will not
switch ■'unless the external field exceeds a certain threshold. This threshold is
attained when the field from the pulsed word line is added to the field induced
by the digit line. If the spot contains a ZERO and a ZERO is to be written, the
external field Induced by the digit winding Is in the same direction as that of the
magnetic film spot and the ZERO remains.
During a READ cycle as shown in Fig. 12-3^, the digit current flows in the same
direction as in the writing of a ZERO. This occurs since the TW flip-flop is
turned off. The read is effected when the word current is tixrned on to aid the
digit current. This switches the ONES to ZEROS. The ZEROS remain as ZEROS and are
not read out. To minimize noise in the sense lines, the sense lines are crossed
between the two arrays. This occasions a bl -polar output. The output of either of
the two arrays must be properly interpreted. This is effected by the strobe unit
which contains a dual transistor strobe circuit. Two gate pulse amplifiers divide
the strobe pulse according to whether the first or second array is used. The PKIR
bit is used to select the proper gate pulse amplifier. Array No. 1 Is selected when
this flip-flop is a ZERO, and Array No. 2 when this flip-flop is a ONE.
12-l6 March 1961
Originally, a "complement" mode of operation was considered which required an extra
transistor circuit in the strobe unit on the ZERO output side. Since this feature
has been abandoned, the complement flip-flop (COMP) output is now tied to the zero
state at all times. Much of the physical circuitry for this mode is still intact
but is not used.
12-5 OPERATION DECODING PROCESS
12-5-1 GEEERAl DESCRIPTION. The paths along which the operation code information flows
are shown on Fig. 12-35- The general interpretation of the six OP code bits in
the instruction word was discussed in Chapters 2 and 7-
The op code bits are transferred sequentially during the instruction execution
from the N register into the PKER register; from the PKER register into the
QKER register; and from the QKIR register into the AKTR register. However,
the picture is quite different for AOP instructions. In these instructions, the
contents of N ^ are transferred directly into the AKER register.
The information in each of these registers is decoded through several levels.
PKIR_p and its associated decoder are used principally during PK cycle operations.
However, they can also be used during QK and AK cycles. The QKIR^p system is used
principally din-ing QK and AK cycles. The AKIR^ system is used only during AK
cycles.
The fact that there are three OP registers permits three different instructions
to be executed simultaneously. An illustration of this situation is shown on
Fig. 12-36. The bar graph in the figure shows the overlapping of several counter
cycles .
12-5.2 OP REGISTER AVAILABILITY FOR DECODING. PKIR , QKIR and AKTR receive their
information, and hence are available for decoding at the following times. The six
.^2a
OP bits in the W register are transferred into PKIR at PK and are available
for decoding in the PK cycle after that time. When the QK cycle starts, the
AK
content of PKIR_ is transferred into QKER^ . During QKIR instructions, the
content of QKIR^ is transferred into AKIR at Qk" . During AOP instructions,
25a
the contents of Wp r- p are transferred into AKTR at PKT" . Thus when AKTR^-
is decoded depends on the instruction.
12-5.3 OP REGISTER 1ST AND 2ND LEVEL DECODING. The first level decoding of each of the
three OP registers consists of a complete decoding of each pair of three bits.
This results in two sets of eight lines. E.g., the PKIR 1st level decoder lines
March 196I 12-17
DECODED FROM DECODED FRCM
PKIRqP 6-U PHRqp 3-1
PKER^^ ™S
The second level OP decoder combines pairs of outputs from the first level decoder
to generate an OP line. E.g.,
PKIR^^^ = PKIRqp • PKIR^
Such OP lines are generated for each OP register, but only as many lines are decoded
as are actually needed.
12-5- ij- CLASS DECODERS. The PKER^ class decoder combines the outputs of the PKIR
register and the first and second level PKIR„p decoders into levels which represent
specific classes of OP codes. These OP class lines are used in level logic, when
it is convenient to represent a class of OP codes exhibiting common properties by
a single level. QKIR„p and AKIR class decoder levels are generated in a similar
manner .
12-5. i;.l PKIR CLASS LEVELS. A brief description of each of these levels is
given below.
E
PKER (FLF, FLG, SPF, SPG) . These OP codes require the use of the
content of a register in the F Memory as an operand.
FF / X
PKIR (SPG, FLG) . These OP codes reqmre the use of the contents
of four successive registers in the F Memory as operands.
T F
PKIR (SPF, SPG) . These OP codes load the F Memory with Memory
Element information.
PKIR (FLF, FLG) . These OP codes store F Memory information in
the Memory Element.
XM XXXIX
P KER (JPX, JNK, JMP, SKX) . These OP codes postpone starting
1 li-CX OK
XWK until after PK . These are PKIR instructions which use an
X Memory operand cycle, i.e., the XWK operand cycle replaces the
QK operand cycle. Other instructions, such as AUX, require a QK
operand cycle.
12-18 March I961
PKrE"^ (CYA, CYB, CAB, SCA, SCB, SAB, NOA, WAB, TLY, ITA, UEA, EXA ,
PSA, IWS, ADD, SUB, MUL, DIV, LDA (-B, -C, -P) , STA (-B, -C, -P) ,
JPA, JWA, JOV and AOP) . These OP codes use the Arithmetic Element.
PKIr'°^ (OPR, JMP, JPX, JI;1X, JPA, JWA, JOV, SKX and the mdefined OP
codes vhose octal nmbers are: 00, 01, 02, 03, 13, 23, 33, k^, ^0
51^ 52, 53, 63 and 73. These OP require no QK operand cycle.
QpTD ATP
PKIR (AOP) . This level is decoded during an OPR instruction
when no deferred address cycles are requested and Np n • ^7*
PHR™^ (LDA (.
-B, C, P, E), STA (-B, -C, -P, -E), SPF, SPG,
FLF,
FLG, ITE, ITA,
OTA, EXA, PSA, INS, SEP, JPA, JTJA, JOV, PCM,
TSP,
CYA, CYB, CAB,
SCA, SCB, SAB, NOA, NAB, TLY, APD, SUB, iTul,
PIv,
^"""^-^JMP, ^^-^^SKX and ^-^^SKX) . These are OP codes in which the
base address is indexed.
I OS
PKIR (lOS) . This level is decoded during an OPR instruction
■when N^ g ' N^ „ .
JX
PKIR (JPX, JNX) . These OP codes specify jump instructions which
are conditional on the X Memory.
PKIR (JPA, JNA, JOV) . These OP codes specify jump instructions
which are conditional on the Arithmetic Element.
PKER^"^^ (OPR, TSP, JMP, JPA, JNA, JOV, JPX, JNX, SEP, SKM and SKC) .
31a
These are OP codes in which PK runs through to PK , i.e., require
a PKEI cycle. (in PKIR instructions, PK runs through to PK .)
PKIR''^'^^ ^^^ (TSP, JPX, JNX, JMP, lOS and SKX) . This class level is
decoded during instructions in which a "dismiss request" is generated.
(The hold bit is not included in the level.) A "dismiss request"
occurs:
1) In a TSP.
2) In an index jump, when the jump condition is satisfied.
3) In an lOS, which has its dismiss bit set (CF ) and which
is not raising the flag of the current sequence (lOS 5OOOO,
with K ) .
k) In a SKX, which has its dismiss bit set and which is not
:-aisir
raising the flag of the current sequence ( SKX, with
March I961 12-19
FKIR^^ (00, 01, 02, 03, 0^, 13. 23, 33, ^3, 30, ^1, 32, 33, 63 ,
73) ■ This 0? code class level is decoded during instructions which
are not defined. This class includes the OPS code {oh) only when
The logic generating the PKIE^^ class levels is shown on Fig. 12-37-
12-5.ij-.2 QKEE CLASS LEVELS. A brief description of each of these levels is
given below. Note that no undefined OP codes ever appear in the QKIR^
register.
FT
QKER (FLF, FLG) • These OP codes store F Memory information in
the Memory Element .
ST
QKIR (STA (-B, -C, -D, -E), EXA, EXX and DPX) ■ These OP codes
perform simple -storing operations in the Memory Element. FLF and
FLG are not included -
QPCTR^^ (LDA (-B, -C, -D, -E) , EXA, EXX, RSX, AUX, ITA, UWA and the
QKIR type OP codes (see below) ) . These OP codes perform simple
loading operations using operands from the Memory Element. Note
that SPF and SPG are not included.
QKIR (ADX, FLF, FLG, INS, PCM, SKM, TSD and QKIR type
i nstructions) . These OP codes include all those which can change
a word in the Memory Element.
LOAD STORE T OAT)
QKIR (QICTR ) . The QKER OP code class level reflects
all the OP codes which do not change a word in the Memory Element
(i.e., QiaR^™^^ OP codes).
QKIR (DPX, EXX, RSX) . These are OP codes which obtain an operand
from the X Memory, but which do not use the X Adder for summing in
this process.
AK"
QKIR (SCA, SCB, SAB, CYA, CYB, CAB, NOA, NAB, ADD, SUB, PSA, MUL,
DIV and TLY) . These are the OP codes which use the AK counter.
12-20 March 1961
QKIR^^^ (SCA, SCB, SAB, CYA, CYB, CAB, NOA, NAB, MUL, DIV and TLY) .
These are the 0? codes which use the AE step counter. Note that
AK
these OP codes are a subclass of the QKIR class.
QKIR (STA, EXA and TLY) ■ These are the 0? codes -which use the A
register as an operand or data register.
QKIR'^ (LDB, STB, INS) ■ See QKER^^ above.
QKIr'^ (LDC and STC) . See QKIR above.
QKIR^ (LDP, STD, ADD, SUB, MUL, DIV, NOA, NAB, SCA, SCB, SAB, CYA ,
CYB and CAB) • See QKTR^ above.
QKIR^ (ITE, IDE, STE and SEP) . See QXIR"^ above.
The logic generating the QKER^ class levels is shown on Fig. 12-38.
12-5.^.3 AKTR CLASS LEVELS. These levels are discussed in detail in Chapter 1^.
12-6 CONFIGURATION DECODING PROCESS
12-6.1 GENERAL DESCRIPTION. The paths along which the configuration information flows
are shown on Fig. 12-39- The CF bits in the instruction word are transferred
from the N register into the PKIR-,-, register. The content of the PKIR register
is then decoded and used to select a word in the F Memory. The selected word
is strobed into the Q,KIR„„ buffer register. The content of the QKIR_,_, register
is then interpreted by various decoders which specify subword forms, activities
and pearmutations . The general interpretation of the five CF bits in the instruction
word in terms of subword form, activity and permutation was discussed in Chapter 2.
12-6.2 SUBWORD FORM. The subword forms in the A, B, C, D and E register during PK and
QK cycles are defined by the value of the bits in QKIR q as shown in Table 12-1.
C-fy,o
March I961 12-21
TABLE 12-1
SUBWORD IWTEEPRETATION OF QKIR
CF9,8
QKIR
CF9,l
FRACTURE (QKIR
SUBWORD FORM
00
01
10
11
■h
36
18,18
27.9
9,9y9,9
A graphical representation of the subword forms is shown in Fig. 12 -4o. Any
combination of subwords of a given form is allowed. E.g., in the (9,9,9,9) subword
form, quarters 3 and 1 can be used simultaneously.
During AK cycles, the subword forms of the data in the Arithmetic Element are
defined by AKLB^^^^q as shown in Table 12-2. Note that in nearly all cases, t
information in AKTR o is a copy of the information in QKTR
^-py.o CF9,8
TABLE 12-2
SUBWORD ITWERPRETATION OF AKTR
'CF9,8
AKTR
CF9,8
FRACTURE (AKIR i)
SUBWORD FORM
00
01
10
11
'^■
36
18,18
27,9
9.9,9.9
12-6.3 ACTIVITY. The "activity" of each quarter in the A, B, C, D and E registers during
PK and QK c;
Table 12-3-
PK and QK cycles is determined by the value of the bits in QKIR^^ , as shown in
CF7-M-
TABLE 12-3
QKIR
CF
ACTIVITY (QKIR^'^^i)
(CF„ CF^ CF CF, )
X X X
X X X
X X X
X X X
ACT,
ACT.
ACT,
ACT,
12-22
March I961
Note that the quarter is "active" when the controlling QKIR flip-flop is a ZERO,
and "latent" (i.e., not active) when the flip-flop is a OEE.
During AK cycles, the quarter activity of the Arithmetic Element is defined by
AKIR„-p^ 1 . Note that usually the information in AKIR_, ^^ is a copy of the
information in QKIRp _i .
TABLE
12
-k
1
AKTR^^
ACTIVITY (AKIR^i)
(CF^
CFg CF^ CF^)
X
X X
1
^1
X
X X
1
^2
X
X X
1
"3
1
%
XXX
12-6.3.1 EXTEHDED ACTIVITY. Subwords can be defined in which not all the quarters
of the subword are active. These are referred to as partially active
subwords. An example of a partially active subword is given in Fig. 12 -4l.
In this example only one quarter of an I8 bit subword is active. Activity
extension is the process by which an entire subword is made active if the
subword is partially active, i.e., activity is extended into the inactive
(latent) quarters in the subword. When the subword form has an influence
upon the execution of an instruction, as in an ADD or MUL, the partially
active subwords are usually made fully active. This is done by nets
which extend the activity of quarters of a partially active subword to
all quarters of the subword. The result is that the subwords are either
wholly active or wholly inactive.
Activity is extended in preparation for sign extension operations in the
Exchange Element. Partially active subwords have inactive quarters filled
by the sign digits of active quarters.
Fig. 12-ij-2 illustrates sign extension for all four subword forms. In
each case the second quarter is active. For an f (36) subword form, the
activity is extended through the third and fourth quarters and then
around through the first quarter. For an f^ (l8,l8) subword form, the
activity is extended around through the first quarter. The subword
containing the third and fourth quarters are not influenced. For an f
(2?;. 9) subword form, the activity is extended through the third and foixrth
qiiarters. The subword containing the first quarter is not touched. For
an f^^ (9}9}9}9) subword form, the activity cannot be extended since each
March 1961
12-23
subword contains only one quarter each. Therefore the three subvords
containing the first, third and fourth quarters are not influenced.
Fig. 12-i]-3 shows the logic generating the extended activity levels.
Level QKIR 1 Indicates how activity can be extended into the first
quarter for various combinations of quarter activities and subword forms.
As an example,
QKIE^ ^^\ = QKrR^^^2 • QKTR^l ' ^2
shows that activity is extended into the first quarter when the second
quarter is active, providing the subword form is f (36) or fp (l8,l8) .
Both these subword forms contain the active second quarter and the
inactive first quarter through which the activity is to be extended.
Subword forms f (27,9) and f, (9^ 9^ 9^ 9) <3.o not appear since the first
quarter is not in the subword which contains the active quarter.
, ^^..EXT ACT- , . X,. +. ^ -, -, nirrr.EXT ACT_ -
Level QKIR 2,1 is a combination of levels QKER 2 and
QKIR 1- It specifies activity in the first and second quarters.
This insures that the first two quarters of the E register are active
during the execution of an exchange index instruction.
ATT APT ATT APT APT
Level QKTR is a combination of levels QKIR 1, QKIR 2, QKIR 3 and
ACTi
QKER h. This level is not actually used any more, but says that the
whole word is active.
Fig. 12-Uij- shows the relationship between a subword form with a specific
activity and the QKIR j levels which are generated.
12-6. k PERMUTATION. The penautation of the operand word in the Exchange Element is
PRM
determined by QKIR . These flip-flops are decoded to generate QKIR i levels.
The eight possible permutations are shown in Fig. 12-^^-5. This figure also illus-
trates the connection between activity in the central computer and in the Memory
Element .
The effective permutation paths between the M register and the E register are
Q^ ^_^-*^ „c3,^_j ^j.iv^.,*^ j.ii J. j.^. j.c_ t^ ■ j.j.jLt; d.^oixa,_i. iuei_ij.cu.ij.i- o wx uiic jjcriuuua uxon proutsss
in the Exchange Element are discussed in Chapter I3.
12-2i4- March 1961
12-6.4.1 PERMUTED ACTIVITY. The permuted activity level QKIR i indicates
that the i-th quarter of memory is connected to an active quarter of the
central machine via the specified permutation path.
Fig. 12-46 shows the logic generating the various permuted acti"vity
levels .
For a specified permuted activity level there are various possible
combinations of permutations and active quarters in the central machine.
As an example,
^j^PRM ACT^ __ Q^^ACT^ . ^^^PRM 3 ^ ^
shows that the first qijarter in memory is active when the second quarter
PRM
of the central machine is active, providing that either the QKIR 3
PPM
or QKIR h permutation paths are specified. Fig. 12-^5 shows that these
are the only two permutation paths possible for this situation.
12-6.5 SIGN EXTENSION. In sign extension, the inactive quarters of subwords are filled
with the sign bit of active quarters of that subword. Inactive quarters to the
left of an active quarter in the subword are first cleared, and then complemented
if the sign bit of the active quarter is a ONE. (See Fig. 12-47-)
The logic governing the clearing of quarters of E under sign extension control is.
SE
-O E • QKIR^ ACT, . Q^^CT. dL^^e., i = 1,2,3,4
The ^Tp E level contains OP code and time level information. The remaining logic
in this level simply says that the given quarter is itself inactive, but that the
quarter forms part of a partially active subword.
If the sign which is being extended is negative, i.e., a ONE, then a complement
pulse must be fired. The logic for these complement pulses is given by.
^ OE • QHR^ ^^\ • QHR^C^i • S. =15 L^^E., i = 1,2,3,4
Here the logic for ' ►E is identical to that for L_--*^ except that it occurs
0.2 microsecond later. S. specifies that Quarter i is itself inactive, but lies
to the left of an active quarter whose leftmost bit is a ONE, where both quarters
are in the same subword and there are no intervening active quarters. The logic
for the S.'s includes the quantitites A, B, C and D. (See Fig. 12-47.) These
quantities are actually the output of a carry-like sign extension net.
March I961 12-25
For example, suppose that the f (36) subword form is specified with quarters 2
1
and k active and E and E, . Then Quarters 3 and 1 will be cleared, since they
have extended activities (see Fig. I2-U3) • Since Quarter 2 is active and ET ,
qiiantity C is generated. This indicates that there is a negative sign to be
extended to the left out of Quarter 2, and causes quantity D to be generated. Note
that since E, and Quarter k is active, quantity A is not generated, and hence
neither is S and S . Of the four S^.'s, only S is generated. Thus, only Quarter
3 of E is complemented under sign extension control. The negative sign of Quarter
2 is extended to the left to fill Quarter 3^ and the positive sign of Quarter h is
extended to the left to fill Quarter 1.
12-7 SEQUENCE SELECTION
12-7.1 GENERAL DESCRIPTION. The Sequence Selector is the unit in the Program Element
which determines whether the next instruction to be executed is taken from the
current program sequence or from some new program sequence.
The components which comprise the sequence selector are:
1) The individual Sequence Selector stages
2) The Priority Patch Panel
3) The K Decoder
k) The J Coder
5) The FLAG register
6) The K^'l '^^ net
7) The K^^ '^ net
The Priority Patch' Panel fixes the relative priority relationships among the
program sequences. As its name implies, the panel is a plugboard with" patch cords
which are used to provide any desired arrangement of priorities among the sequences.
The Sequence Selector stages determine which is the highest priority sequence
desiring attention. The Priority Patch Panel of course influences this decision.
The K Decoder provides the Sequence Selector with the number of the current sequence
being executed.
The J Coder encodes the thirty-three outputs of the sequence selector stages and
specifies the number of the next sequence. The encoded number can then be inserted
into N g _ , the J bits in the N register.
The FLAG register indicates which sequences request attention. It contains one
FLAG flip-flop for each of the 33 program sequences.
The two nets on the K register compare the number in the K register with the
output of the J Coder and the number in the J bits.
12-26 March I961
12-7-2 PRIORITY PATCH PANEL. This panel consists of a plugboard with t-wo sets of 3 X 33
jacks. One set of jacks is associated with the priority number. The other set of
jacks is associated with the Sequence Selector stages.
The Priority Patch Panel, as shown in Fig. 12-48, is divided into four sections.
Three of the sections are each composed of eight stages which coincide with the
Sequence Selector stages. Section 3 has 9 stages instead of 8 stages due to the
startover sequence. Each stage of the Priority Patch Panel contains two sets of
three jacks. The upper set of jacks of each stage are interconnected throughout
a section.
One jack from each stage is connected in parallel. The other two jacks are
connected in series. The series connections are used to transmit infonnation
serially through a section (with the initial input tied down to represent no
information coming in) . The parallel connection is used to feed information in
from outside a section simultaneously to all stages in a section. The output
from the last stage of the series connections of section represents the only piece
of information coming out of a section. These outputs are connected as shown to
all lower priority sections and to a last OR net to generate the SS' level.
Note that the input to the parallel connection of section 3 (the highest priority)
is also tied off to represent no information. The effect of all these connections
is that attention request information generated by any Sequence Selector stage is
transmitted through at most one full section (8 stages) before contributing to
ATT "R"FO
the SS level. Two full sections (l6 stages) is the maximum delay met before
such information gets to any other lower priority Sequence Selector stage. (This
should be compared with a maximum delay of 32 stages in a wholly serial net.)
The lower set of three jacks in each stage of each section is connected to the
corresponding Sequence Selector stage.
The priority of a given Sequence Selector stage is determined by which (upper) set
of three jacks is connected to the (lower) set of three jacks of the Sequence
Selector stage- The upper set of three jacks may be in the same section as the
lower set of three jacks or even in another section. All these interconnections
are accomplished by patch cords and can be changed whenever the need arises.
12-7.3 SEQUENCE SELECTOR. The Sequence Selector consists of 33 stages. All of the stages
are identical with the exception of the first stage. The first stage corresponds
to the Startover Sequence (octal OO).
Fig. 12-^9 illustrates a typical stage of the Sequence Selector.
March 1961 12-27
There are three levels that the Sequence Selector may generate. They are SS
, _„CH SEQv „„NEXT SEQ ^ ^^ATT REQ
(or SS j ^ SS and SS
The SS level is generated by ORing the PP ^^ outputs from the patch
panel sections. These outputs from the patch panel are formed by cascodlng within
Arnrp ■pTpQ
the individual sections, the SS* inputs from the Sequence Selector stages.
%} h; h
These individual inputs state that either the flag of a sequence, -which is not the
current sequence, is up; or that some sequence of higher priority within the same
quarter requests attention. Note that if the highest priority stage in a quarter
requests attention, it must cascade through, at most, 8 other stages before contri-
buting to the SS level. Note also that when the current sequence is in a
"waiting" state and no instructions are being executed, then KD is disconnected
ATT Rl^O
from the K register and SS can indicate whether the current sequence requests
attention also.
The SS " level indicates whether a sequence of higher priority than the current
sequence has its flag up. This level is used to determine whether a change of
sequence to a higher priority sequence can occur when the hold bit on an instruction,
being executed in the current sequence, is a ZERO. This is generated by ORing the
SS levels produced by the Sequence Selector stages. Only one of these levels,
the one coming from the current sequence, can ever be on, and even this cannot
occ\jr unless KD is connected to K. The individual levels are generated by simply
determining whether the attention request levels, coming in from the priority panel
connections, state that a higher priority sequence requests attention. The maximum
PIT ■R7?Q
delay met by attention request information before contributing to the SS"
level is two full sections (l6 stages) .
The SS levels are generated by the individual selector stages. Only one,
at most, of these can be turned on at a given time. If one is on it indicates
that the corresponding sequence is the highest priority sequence with its flag
raised. The level is formed in a selector stage when the flag is up but no sequence
of higher priority requests attention. The current sequence, identified by the KD
level, is usually excluded.
The Startover Sequence Selector stage is similar to the others-, except that it can
occupy only the highest priority position. (See Fig. 12-50.)
All the Sequence Selector stages contain logic to complete the decoding of the
^3.6 - 3.1 '^'^^^' "^^^ circuitry is called the N Decoder, even though its inputs
are N g and JD. The outputs go to the In-Out Element.
12-28 March 1961
12-7.4 FLAG REGISTER. The FLAG register is composed of 33 flip-flops, one for each
sequence. Each flip-flop is set, i.e., each flag is raised, when its associated
in-out imit re(
in Fig. 12-51.
in-out unit requests attention. This is indicated by the ' ^- FLAG pulse shown
Certain instructions can also affect the flag of the sequence specified by the
N g _ bits of the instruction. An lOS instruction can raise or lower (clear)
a flag if bits W g _ p < in the address section have the value 101 or 100,
respectively. An SKX can raise a flag if PKrR__, . All the pulses which do this
260; ii
are gated by KD and occur at PK
Another group of pulses which are gated by KD can also lower flags. However, the
gating by KD means that only the flag of the current sequence is affected. These
pulses are called "dismiss" pulses. Whenever a change of sequence is made to
sequence 00, the Startover Sequence, the flag is lowered in order to allow pulses
from the Startover button to recognize which sequence 00 is running. This pulse
occurs at CSk . If the computer attempts to execute a TSD and either it is still
executing a previous TSD, or it finds the In-Out unit of the sequence is busy, then
P20!
it will lower the flag. This pulse occ\h-s at PK and is called "dismiss and
wait". The other pulse of this type occurs during an ordinary "dismiss". Here
the pulse is given at PK -^ during instructions which request a dismiss (PKIR''^"'"^ ^"^'^)
in sequences other than sequence 00. This last exclusion exists because the dismiss
pulse for sequence 00 was given at CSIT-^ when the sequence was entered and a new
flag raising in this sequence might have occurred while sequence 00 was running.
I PRESET
Another level that clears the flags is the ' ^-^ SS level. This level is
generated by the start-stop control.
12-7.5 K DECODER. The K Decoder interprets the K^ g bits. It generates 33 lines,
one for each of the Sequence Selector stages. These lines also go to the In-Out
units. The K ^ bit is used for a special purpose. K^ . • (CSK^ • PK^^) is
substituted for the KT g input to the K Decoder. This logic says that when the
current sequence is not sequence 00, and the computer is waiting (CSKf) after an
ordinary dismiss (PK"^ ), then the K Decoder is disconnected from K, i.e., KD ^ K.
This logic permits the Sequence Selector to request the raising of the flag of the
current sequence, after it has been dismissed.
12-7.6 J CODER. The J Coder serves the function of encoding all the SS^^ ^^'^ levels
into the six bits to be inserted into the N g bit position of the N register.
March I961 12-29
12-7-7 K^^ '^'^ WET- This net determines whether the number of the current sequence is
the same as the highest priority sequence vhich requests attention. This information
is used when the wait cycle (DSK) ends because some sequence wants attention and
the possibility exists that this situation might exist because KD was disconnected
from K (KD / K) .
12-7-8 K^^ KET- This net determines whether the contents of K and J are eq-ual- It is
used, for example, to determine whether lOS and SKX instructions are raising the
flag of the current sequence at the same time that they are dismissing. In these
cases the PKIR level is not generated.
]_2_30 March 19 6l
4^
f
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CHAPTEE 13
EXCHMGE ELEMMT
TABLE OF CONTENTS
13-1 INTRODUCTION
13-2 M REGISTER (OPERAND MEMORY BUFFER)
13-2.1 OPERAND MEMORY STROBE
13-2,1.1 PARITY BIT (2.10)
13-2.1.2 PARITY ALARM
13-2.1.3 META BIT (i^-.lO)
13-2.2 E TO M TRANSFERS
13-2.2.1 ^H,^3^,^^
13-2.2.2 E ^,^ » . M AND E
CYL CYR ^
13-2.2.3 E QA^ M
13-3 E REGISTER
13-3.1 xM TO E TRANSFERS
13-3.2 ARITHMETIC ELEMENT TO E TRANSFERS
13-3.3 lOBM TO E TRANSFERS
13-3-^ MISCELLANEOUS USES OF E REGISTER
13-3.5 INTERCHANGE OF E REGISTER QUARTERS
13-3-6 CLEAR AND COMPLEMENT E REGISTER
13-^ ILLUSTRATIVE EXAMPLES
13-4.1 LOAD TYPE INSTRUCTION
13-^.2 STORE TYPE INSTRUCTION
13-^.3 SIGN EXTENSION
LIST OF FIGURES
13-1 MEMORY STROBE INTO M REGISTER
13-2 MEMORY STROBE INTO M REGISTER REGISTER DRIVER LOGIC
13-3 REGISTER DRIVER LOGIC OF M AND E REGISTERS FOR SKM INSTRUCTION
13_1| TRANSFER LOGIC FROM E TO M DURING TSD
13-5 E ► M, M REGISTER RD CONTROL
13-6 CYCLIC REGISTER TRANSFER BETWEEN REGISTERS E AND M
13-7 M ► E, E REGISTER RD CONTROL
13-8 ARITHMETIC ELEMENT REGISTERS TO E RD CONTROL
13-9 MISCELLANEOUS E REGISTER RD CONTROL
13-10 E REGISTER PERMUTATION RD CONTROL
13-11 ' » E, I ► E E REGISTER RD CONTROL
13-12 CONFIGURED LOAD TYPE INSTRUCTION ILLUSTRATING BASIC PERMUTATION AND M ». E TRANSFERS
13-13 CONFIGURED STORE TYPE INSTRUCTION ILLUSTRATING BASIC PERMUTATION AND M ► E TRANSFERS
13-1^ SIGN EXTENSION IN E REGISTER
13-15 CONFIGURED LOAD TYPE INSTRUCTION ILLUSTRATING SIGN EXTENSION
March I961 ]_3_]_
CHAPTER 13
EXCHMGE ELEMENT
13-1 IIWRODUCTIOW
During the execution of an instruction a complex series of data transfers may take place
in the Exchange Element. Both the transfers themselves and the order in which they occur
is important in determining the net effect of the transfers. This chapter will emphasize
the register driver logic for the individual transfers and mention only in passing the time
ordering of a sequence of transfers. A detailed dynamic picture of the transfers is devel-
oped in Chapter 16.
Manipulation of data in the Exchange Element involves the following register driver pulses:
10^ ^ Q_^ or L^ pulses to \^j^^^^^ or \^j^^^^^
M. — ^-•►E.; M. — ^E.; M.- — a-^E. \. (i = 1,2,3.^)
1 1 1 1 1 1 '
E. ^». M. j E. — ^M.; E. j »■ M.
i 11 i"^ 1 1
E. ^ ► E. ^
L (p = 1>2,3; where 3+1=0, 3+2=1, etc.)
E. *- E. _^ J
1 1 + p -^
E "^ »- M (CYR = cycle right)
CYE
E-^^-^M (CYL = cycle left)
CYL
I C^
pulses to M, (M, = meta bit)
In addition to the above, there are register driver pulses which transfer the contents of
registers in other elements into the E and M registers.
Normally, data transfers occur in the Exchange Element during an operand cycle. This means
that the transfer pulses are usiially initiated by a QK time level. The following are
exceptions to this rule:
1) If an instruction word is read out of the V Memory, information will be trans-
ferred through the Exchange Element during the instruction cycle. Hence the
transfer pulses will be initiated by PK time levels.
13_2 March I961
2) The following Instructions may temporarily store data in the E register during a
PK cycle for reuse at a later time in the instruction:
lOS
JMP
JPX and JICC
Data may also be stored temporarily during deferred addressing (PK) and during a
change of sequence (CSK).
3) During the execution of the SPF, SPG, FLF and FLG (F Memory) instructions, the
FK counter initiates several data transfers in the Exchange Element.
13-2 M REGISTER (OPERMD MEMORY BUFFER)
Data is transferred into the M register from either the E register or the Memory Element.
There are no other transfer paths into the M register.
13-2.1 OPERMD MEMORY STROBE. Fig. 13-1 shovs the logic involved in strobing a vord out
of the Memory Element. The strobe logic for M and W are similar and is covered in
greater detail in Chapter 11. The data may be transferred from a given memory
sense amplifier into either the M or N register. If an instruction word is involved,
it will be placed in the N register during a PK cycle. In the case of an operand,
the word is placed in the M register during a QK cycle.
The operand strobe pulse logic is shown in Fig. 13-2. This logic consists of an
operand memory selection level and a QK time level. The operand is strobed at
QK" . In the case of the S Memory, the strobe pulse is routed through a "ripple"
delay line. Thus, although the pulse is initiated at QJC , it does not finish
strobing until QK
13-2.1.1 PARITY BIT (2.10). The parity bit is read out of memory into the M
register along with the other operand bits. However, it is not written
into memory with the other M register bits.
Before the content of the M register is written into memory, the parity
of the word in the M register is computed. The output of the compute
parity circuit is written into memory in place of the Mp bit. Once
the M register is cleared, the original parity bit is permanently lost.
During a normal load type instruction, the output of the check parity
circuit will be equal to the IVU -,q bit if there is no read error. However,
if a bit of the word is lost during the memory strobe, a parity alarm
flip-flop (MPAL) will be set, since the check parity will not equal the
value of the VL bit in this case.
March I961 13-3
13-2.1.2 PARITY ALARM. Normally, if the parity alarm flip-flop (MPAL) is set, the
content of the M register should not be destroyed. (The operator may
n-ullify the effects of this alarm by means of the parity alarm suppress
pushbutton (MPAL ) . ) However, the condition of the check parity circuit
must be ignored at certain times, e.g., just before memory strobe when M
contains all ZEROS. For this reason, a parity alarm level (MPA) is gen-
erated which controls the M register driver logic. If MPA is generated,
then no pulses are allowed to change the content of M.
This MPA circuit looks at MPAL, MPAL^ and the parity alarm inhibitory
logic involving MPS. The net effect is that MPAL • MPAL is a nee-
essary but not s-ufficient condition for MPA. Pulses generated between
Qiv and QK are always allowed to change the content of M.
13-2.1.3 META BIT (4.10). This bit is read into the M register from the Memory
Element with the other operand bits. It is rewritten into memory, just
as it was read out, for all instructions except SKM. The SKM instruction
may complement, set to ONE, or clear to ZERO M> before the contents of
Ml are rewritten into memory.
Fig. 13-3 shows the register driver logic for complementing, setting or
clearing the meta bit under SKM control. The state of the PKIR^_ and
CF^
PKER_^ bits determines which modification of the meta bit will take
CF^
place. Note that the meta bit cannot be modified unless the memory parity
alarm level is absent, i.e., an MPA condition exists. During an SKM
instruction, the q^uarters of E are complemented, cleared, and set by the
same register driver logic (except for the parity alarm inhibition) that
correspondingly modifies M, .
The second term in the ' — ►M, register driver logic indicates that
the meta bit is cleared when the M register as a whole is cleared, except
in those cases where the M register is cleared at QK" . The QK"
inhibition guarantees that the meta bit will be rewritten in memory just
as it was read out xmless an SKM instruction is being executed. During
most instructions, the meta bit will be cleared at QK^"^ by the following
logic:
It should be realized, however, that M, is cleared by special circuitry
and not in the direct manner indicated by the above equation.
The operand meta bit can be transferred between the Memory Element and
the M register only.
13-4 March I961
13-2.2 E TO M TRMSFERS. The register driver logic tabulated on Fig. 13-5 indicates the
various conditions under which E to M transfers take place. The conditions are
determined by: the OP decoder class levels, which indicate in what instruction or
type of instruction the transfer occurs; the time levels, which determine when the
transfers occur; and the levels reflecting configuration control, sign extension
control, parity, alarm control, etc.
■ Certain lOCM (in-Out Control Mixer) level logic associated with the TSD instruction
is found on Fig. 13-5. Tiiis logic is discussed in detail in Chapter 15- Fig. 13-ij-
siiramarizes the aspects of this logic that are important in the discussion that
follows. Note that only the lOCM logic (which indicates a TSD is transferring
data between the In-Out Element and the central computer) is involved. Data may
be transferred in both the NOEMAL and ASSEMBLY mode during a TSD, In the NOMAL
mode, data from the In-Out Element is transferred from E to M under config-aration
control, while in the ASSEMBLY configuration control is not used. Instead the data
is cycled (shif ted) one pl ace to the right if an lOCM^ level is present, or to
the left if, an lOCM^ level is present, during the E to M transfer.
13-2.2.1 ' — ^ M) _ • This clear pulse occurs whenever the parity alarm inhi-
bition is absent (MPA) and any one of the following three conditions is
satisfied:
1) The instruction is a TSD in the ASSEMBLY mode.
2) The instruction is an SKM and PKTE is a ONE. (Note that this
condition is not sufficient to clear M, •)
3) All instructions having an operand cycle will normally clear the
M register at QIC , except those using the V__ Memory during
the operand cycle. Thus, TSD and SKM may clear the M register
twice during the QK cycle.
13-2.2.2 E ►M AM) E ► M. Conditions 1 and 2 above, which cleared M at
CYL CYR
QK , also cycle E into M at QIT^. The only difference in the clear
and cycle logic is the parity alarm condition and the added control logic
for determining whether the shift is to the right or left. (See Fig.
13-6.)
13-2.2.3 E — ► M. There are three categories of conditions under which this
transfer takes place:
1) Broadside Transfers . Certain types of instructions transfer the
ZEROS and OlffiS of all the quarters of E into the corresponding
quarters of M simultaneously. These instructions include FLF,
FLG, COM, and instructions involving the V„„ Memory.
Fr
March 19 61 13-5
2) Transfers Under Permuted Activity Control . In this case, the
pulses on the gates between each quarter of E and M are inde-
PRM ACT
pendently controlled by QKIR i levels. The contents of E
are transferred to M under permuted activity control during all
the store type instructions at Qk . In the case of the INS
instruction, the ZEROS are transferred at QK -^ and the ONES are
transferred at Qk -'^. Even though the store type instruction's
are included, these instructions do not go through QIC , so
that this condition is satisfied by only a few instructions.
If a TSD is executed in the NORMAL mode or if PKIR^_ is equal
CF3
to ONE during an SKM instruction, the logic is satisfied and an
E to M transfer occurs under permuted activity control.
3) Transfer of ZEROS from E to M . This is one of the Exchange
Element transfers involved in the execution of the ELF instruction.
13-3 E REGISTER
The following types of transfers into the E register can take place:
1) Data can be transferred from the M register into the E register.
2) Data can be transferred from the A, B, C and D register into the E register.
3) Data in the lOBM (in-Out Buffer Mixer) can be transferred into the E register.
k) Data from the P, Q and XA registers can be transferred into the E register.
5) Certain bits of miscellaneous registers can be transferred into the E register for
temporary storage.
In addition to the above, the quarters of E can be independently cleared and complemented,
and the data in the quarters can be permuted.
13-3.1 M TO E TRANSFERS. The register driver logic for these transfers is shown in
Fig. 13-7' It falls into three general categories.
1) Transfers Under Permuted Activity Control . Just as store type instructions
transferred data from E to M at QK , load type instructions transfer
data from M to E at QK"~^ . Note that a TSD or an SKM instruction may also
transfer data from M to E at QiC .
The ADX instruction has some of the characteristics of a load type in-
struction and some of the characteristics of a store type instruction.
For this reason, it is treated separately and not lumped with the store
type instructions.
13 _6 March 1961
During the execution of an ITE instruction, the ZEROS of M are transferred
into E at QK^*^, but not the OKES.
2) Broadside Transfers . A jam transfer from M to E will occur for most store
type instructions at Q^ and for most load type instructions at QK .
COM, SPF, SPG or a TSD in the ASSEMBLY mode causes a jam transfer to
occur from M to E at QiC"-^ ,
In addition to the above, a jam transfer from M to E occurs whenever the
V^^ Memory is involved.
JLlo;
Finally a jam transfer from M to E occurs at PKT" during a deferred
address cycle.
3) "Exclusive or" Transfer between M and E Under Permuted Control . This
transfer occurs twice during an SED instruction. The second transfer has
the effect of restoring the E register to its original state because of
the logical characteristics of the "exclusive or".
13-3.2 ARITHMETIC ELEMEHT TO E TRANSFERS. The register driver logic for these transfers
is shown in Fig. 13-8. Two cases exist: either the V Memory is or is not
involved in the instruction.
1) In the first case, if an instruction is stored in either the A, B, C or
D registers, the instruction word will be read into the E register at
PK . Note that if tlje Arithmetic Element is busy, PK will not get to
PK until the AEB condition is satisfied. If an operand is stored in
the Arithmetic Element and that element is not busy, the operand will be
read into E at
QK^3«
2) The second case includes load and store type instructions involving the
Arithmetic Element registers. In the case of INS, ITA and UNA, data is
transferred specifically from the A register to the E register.
13-3*3 lOBM TO E TRANSFERS. During the execution of a TSD in the IN mode or during the
execution of an lOS when PKIR„_ is a OWE, a jam transfer occ-urs from the selected
CF^
lOBM. (in-Out Buffer Mixer) to E. The register driver logic for this transfer is
shown in Fig. 13-9-
March I961 13-7
13-3'^ MISCELLANEOUS USES OF E REGISTER. Fig. 13-9 also shows the register driver logic
involved in several miscellaneous transfers into E. The transfers occur:
1) During a deferred address cycle, when the content of QfCER-,^ is placed
in E^ ^ „ ^, and the content of XA (X Adder register) is placed in E .
3.0 - 3.1 c,x
2) During a change of sequence cycle, when the content of I-L g _ _ _ is
placed in E g ; the content ofiCg_is placed in Ej^^g _ ^^^,
and the content of P is stored in E .
3) During the X Memory instructions, when the content of XA is placed in
^2,1-
k) During a JMP instruction (if PKIR„„ contains a ONE) when the content of
Q is placed in E . Also during a JMP (if PKIR „ contains a ONE), when
the content of P is placed in E, .
5) During an lOS instruction (if PKIR_,_ contains a ONE), when the content
CF^
of N.
3.6 - 3.1 "' ^^^"^'^ ""^ ^3-6 - 3.1-
6) During a JPA, JNA or JOV instruction (if the jump conditions are satisfied),
when the content of P is placed in E^ .
7) During a FLF or FLG instruction, when the content of QKTR^-r, is placed
^^9-1
^^ \.9 - k.l
13-3'5 INTERCHANGE OF E REGISTER QUARTERS. The register driver logic for this inter-
change is shown in Fig. 13-IO.
There are two general circumstances in which the quarters of E are interchanged.
In one case, the interchange is a by-product of configuration control and is
indirectly imder the control of the programmer. The programmer may select one of
several configurations for the same basic instruction. The interchanges in the
E register for the configuration will then take place. In the second case, the
interchange is a basic step in the instruction. During store aoid load type in-
structions involving the F Memory (SPF, SPG, FLF and FLG), the quarters of the E
register aire interchanged in such a way as to cycle the content of the E register
either one quarter to the right or one quarter to the left. The interchange is
initiated by the FK counter.
13-8 March I961
Several observations can be made by looking at the individual terms for directly
and inversely permuting the quarters of E. First observe that most of the in-
structions are included in the Qk ' , Qii and QK tenns. However, while the
load and store type instructions go through QIC and Qiv , they do not go
through QK . Thus, the QIC" term will include far fewer instructions than the
factor MDed with QK . Note that, in most configured instructions, both an
inverse and direct permutation will occur.
13-3.6 CLEAE AND CaMPLMEKT E REGISTER, These operations are involved in combination in
the process of sign extension (see Fig- 13-11) • ^e logic involved in extending
the sign of an active quarter into the inactive quarters of a partially active
subword causes the inactive quarters to be cleared at QK . If the sign bit of
the active quarter is a OWE, the inactive quarters are then complemented at QK .
The sign extension control teirm of the register driver logic includes factors which
take into account the activity and coupling involved in the instruction.
In the case of the CCM instruction, the sign is extended at QK , and then the
active quar-ters themselves are complemented at QK . During an INS or ITA
instruction, the content of the entire E register is complemented as a basic step
in the execution of the instruction.
Earlier in the chapter, it was mentioned that the content of XA is copied into
E at QK , during the execution of X Memory type instructions (RSX, ADX, EXX
^^1
or DPX). If the sign bit in XA (X ) is a ONE, E, will be complemented at
QK^ as part of the sign extension logic in the E register. Effectively, the
content of the X register is extended to fill the E register.
Certain miscellaneous instructions require that the E register be cleared before
a data transfer into the E register can take place. This occurs:
1) For most instructions using QK in an operand cycle.
2) As a preliminary step to N /- ^^-3 fi -i ^> during an lOS when
PKTR^^ is a ONE.
CF^
3) For all instructions involving the V^^^ Memory, except when the instruction
ss
is placed in E.
W) As a preliminary step to placing data in E, during a deferred address
cycle .
5) As a preliminary step to placing the contents of Q in E, during a JMP
instruction when the PKrR^_ bit is a ONE.
CF^
March I961 ^3-9
13-^ ILLUSTRATIVE EXAMPLES
Some examples will be given to illustrate the use of the register driver logic tabulations
given in this chapter. These examples illustrate the configuration and sign extension
operation which is processed in the Exchange Element. In these examples, the transfers
that occur in the Exchange Element during a configured load and a store type instruction
will be examined. Only those transfers illustrating configuration will be examined in
detail.
In the example, it is assumed that the programmer specified a configuration that caused
the third quarter to be inactive and that calls for an f (l8,l8) subword form. The
specified configuration makes use of permutation 3-
This permutation has the effect of shifting the quarters of M one quarter to the left into
the E register, d\jring load type instructions; and the quarters of E one quarter to the
right into M, during store type instructions. In the example, it is also assumed that the
sign bit of the active quarter of the partially active subword is a OWE in the load type
instruction.
Let m. and e. represent the original contents of the quarters of the M and E registers,
respectively.
For the exan5)les cited, the configuration bits are as follows:
QKIR^^ I 01 0100 Oil
Coupling: l8,l8
Permutation: 3
Third Quarter:
Inactive
13-^.1 LOAD TYPE INSTRUCTIONS. The load type instruction will be examined first. Fig.
13-12(a) shows the effect of the instruction (neglecting the effects of sign
extension) on the M and E registers. At the end of the instruction, the operand
appears in M just as it was read out of memory. The E register contains the word
in M shifted one quarter to left, except for the third quarter of E which contains
whatever was in E before the instruction began.
The sequence of transfers that accomplishes this operation is as follows:
l) Fig. 13-2 indicates that the operand is usually strobed out of memory
into M at Q,^'^^ .
13-10 March 19 6l
2) Figs. 13-10 shows that at Qk ^ E is also inversely permuted. This can
be seen since the "OP" and "CF" bits are decoded to generate QKIER and
PRM
QKIR 3 levels. If -we assume that this is not a SPF or SPG instruction^
then the logic on Fig. 13-10 is satisfied and all the quarters of E -will
be shifted one quarter to the right at QIC , I.e., E will be inversely
permuted.
3) Figs. 13-7 and 13-12 (c) show that a transfer will occin- from M to E under
permuted activity control at QIC . All quarters of M are transferred^
except the second quarter. This selection occurs because of the
pPM APT
QKIR 2 level in the transfer logic. This level is generated by
logic that looks at both the permutation and activity required by the
instruction and decides in which quarters an M — ►E transfer should occur.
Note that E now contains the correct data but the data is all shifted one
quarter to the right.
k) Figs. 13-10 and 13-12 (d) indicate that at QIC-^^ (0.2 microsecond after the
M — ^-E transfers) a direct permutation occurs in which data is finally
shifted to the left into the desired quarters. Compare the E register in
Figs. 13-12 (a) and (d) .
The sign extension process which follows step h is described in 13-^.3.
13-4.2 STORE TYPE INSTRUCTIONS. The store type instruction will now be examined. Fig.
13-13(a) shows the effect of the instruction on the M and E register. The M register
contains the content of the E register shifted one quarter to the right, except for
the second quarter of M which contains whatever data was in it at the beginning of
the instruction.
The sequence of transfers that accomplishes the store instruction is as follows:
1) If the instruction is STA, the content of A is placed in E at QK as
indicated on Fig. 13-8.
2) Figs. 13-13(b) and (d) are exactly the same transfers and occur at exactly
the same time as the transfers shown in Figs. 13-12 (b) and (d) .
3) Figs. 13-5 and 13-13 (c) indicate that a transfer -under permuted activity
control from E to M occurs at QK . Note that at the end of this transfer,
M contains the word that is to be stored in memory. E however must still
be unscrambled by the direct permutation pulse that occurs at QIC
March 1961 13-11
Thus, neglecting sign extension, the basic difference between a store and load type
instruction, as far as the Exchange Element is concerned, is the transfer piilse
occurring at Qk . In the store case, QIC initiates an E — ^- M transfer. In
the load case, QK initiates an M — ►£ transfer.
13_ij..3 SIGN EKTENSION. Fig. 13-1^^- shows the basic concept of sign extension as it applies
to the E register. The general rule for extending the sign is also given.
Fig. 13-15 gives a specific example of sign extension. This figure is in reality
an extension of Fig. 13-12. The E register was permuted at Qk -^ on Fig. 13-12(d).
Fig. 13-15 (a) shows that the third quarter of E is cleared at Qk . For the case
ACT
chosen, the fact that the fourth q-uarter of E is active (QKIR k) and the coupling
is f (f II' f^) generates the QKTR 3 level. The logic for clearing E is
shown in Fig. 13-15 (a)-
At QK , the sign of the active fo-urth quarter is extended into the inactive third
quarter by the simple operation of complementing the third quarter of E. The
operation and the complement logic are shown in Fig. 13-15 ("b). Note that, if the
sign bit of the fourth quarter were a ZERO (E, ), then the complement pulse would
not have occurred and the inactive third quarter wotild have been left with all
ZEROS in it.
13_12 March I961
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CHAPTER Ik
ARITHMETIC ELEMENT
TABLE OF CONTENTS
li<-l INTRODUCTION
lll-2 ARITHMETIC ELEMENT INSTRUCTION CLASSIFICATION
llj-2.1 AK TYPE INSTRUCTIONS
lij-2.2 AK TYPE INSTRUCTIONS
1^1-2.2.1 Z FLIP-FLOPS
lij-2.3 ASK TYPE INSTRUCTIONS
llj-2.3.1 ADD AND SUB
lij-2.3.2 DSA
lif-2.q- ASK TYPE INSTRUCTIONS
li|-2.5 COUNT IN D TYPE INSTRUCTIONS
1^4-2 . 5 . 1 MULTIPLI CATI ON,
14-2-5.2 DIVISION
lij-2.6 COUNT IN D TYPE INSTRUCTIONS
1^1-2.6.1 SCA, SCB, SAB, CYA AND CAB
14-2.6.2 NOA AND NAB
14-2.6.3 TLY
AF Afr
14-2.7 OPR VS OPR ARITHMETIC ELEMENT INSTRUCTIONS
l4-3 ARITHMETIC ELEMENT REGISTER OPERATION
14-3.1 STANDARD TRAJ^SFERS
14-3
14-3
14-3
14-3
2 SPECIAL LOGICAL TRANSFERS
3 D REGISTER COUNTER
4 SHIFTING OPERATION
5 CARRYING OPERATION
l4-4 ARITHMETIC ELEMENT LEVEL LOGIC
14-4.1 AKIR_^ AKIR^^ REGISTERS
OP CF
14-4.1.1 AKIRqp DECODING
14-4.1.2 AKTR^^ DECODING
1
14-4.2 ALL ZEROS (AT), ALL ONES (AT) LEVEL LOGIC
l4_4.3 SIGMA (cr ) LEVEL LOGIC
14-4.4 SHIFT COUPLING UNITS
14-4.5 CARRY COUPLING UNITS
14-4.6 AEJ LEVEL LOGIC
14-4.7 1^ ♦AEP LEVEL LOGIC
l4-5 ARITHMETIC ELEMENT REGISTER DRIVER LOGIC
14-5.1 ~d1 + 1 ►D. RD LOGIC
i' 1
14-5.2 A REGISTER SHIFT RD LOGIC
14-5-3 B REGISTER SHIFT RD LOGIC
14-5.4 MULTIPLY STEP RD LOGIC
14-5.5 COMPLEMENT C RD LOGIC
14-5.6 CARRY RD LOGIC
March I961 l4-l
ll|-5.7 PARTIAL ADD ED LOGIC
li^-5.8 A, B, C AMD D CLEAR RD LOGIC
14-5-9 Z PULSE GATE AJTO RD LOGIC
1I+-5.IO A REGISTER COIPLEMEWT RD LOGIC
lij-5.11 B REGISTER COiMPLEMEKT RD LOGIC
14-5.12 D REGISTER CCMPLEMEOT RD LOGIC
14-5.13 E-*^A, B, C AUD D RD LOGIC
l4_5.l4 A j »■ B AMD B j » ■ A RD LOGIC
LIST OF FIGURES
l4-l AE INSTRUCTIONS CLASSIFIED BY COUIWER ACTIVITY
l4-2 FUNCTIONAL BLOCK DIAGRAM OF THE AE FOR AK TYPE INSTRUCTIONS
l4-3 FUNCTIONAL BLOCK DIAGRAM OF THE AE FOR AK TYPE INSTRUCTIONS
l4_4 EFFECT OF AK TYPE INSTRUCTIONS ON Z FLIP-FLOP
l4-5 ADDITION OVERFLOW LOGIC
l4-6 SAB EXAMPLE SHOWN FOR f FRACTURE AND POSITIVE AND NEGATIVE OPERAND SUBWORDS
l4-7 CAB EXAMPLE SHOWN FOR f^ FRACTURE AM) POSITIVE AITO NEGATIVE OPERAND SUBWORDS
l4-8 FUNCTION OF ASK AND D COUNTERS IN ASK TYPE INSTRUCTIONS
l4-9 AE REGISTER FUNCTION FOR AK TYPE INSTRUCTIONS
l4-10 AOP AND A^ AE INSTRUCTIONS
14-11 TYPICAL AE REGISTER OPERATIONS
14-12 JAM TRANSFERS BETWEEN A AND B
14-13 TRANSFERS GATED BY '^^ ^ PULSE
l4-l4 TRANSFERS GATED BY L^UL STEP ^ -puLSE
14-15 D REGISTER COUNT CIRCUIT
l4-l6 A REGISTER SHIFT LOGIC
14-17 A REGISTER GARRY LCK}IC
l4-l8 AKER 1ST LEVEL DECODERS
14-19 AKIRqp OP DECODERS
14-20 AKTRqp CLASS DECODER
14-21 AE CONFIGURATION LOGIC
14-22 A. ALL ZEROS, ALL ONES NETS
1 '
14-23 SIGMA LOGIC
14-24 A SHIFT COUPLING UNIT LOGIC
14-25 B SHIFT COUPLING UNIT LOGIC
14-26 EXAMPLES OF SHIFT COUPLING
14-27 CARRY COUPLING UNIT LOGIC
l4-28 EXAMPLES OF CARRY COUPLING
14-29 AE JUMP NET LOGIC
14-30 L^ AEP LOGIC
14-31 AE RD PULSES
14-32 AE PULSE GATE LOGIC
14-33 D COUNTER RD LOGIC
1^-2 March I961
lk-3h A REGISTER SHIFT RD LOGIC
lij-35 B REGISTER SHIFT RD LOGIC
1^-36 MULTIPLY -STEP RD LOGIC
ill -37 C(MPLEMEIW C RD LOGIC
llj-38 CARRY RD LOGIC
14-39 PARTIAL ADD RD LOGIC
ik-kO CLEAR A, B, C AND D RD LOGIC
ll|-4l Z PULSE GATE AND RD LOGIC
llj._ll2 COMPLEMENT A RD LOGIC
llj._43 COMPLEMENT B RD LOGIC
ik-kk COMPLEMENT D RD LOGIC
ik-k^ E "^^ A, B, C, D RD LOGIC
ik-kS E j » .B AMD B &-^A RD LOGIC
March 1961 14-3
CHAPTER lU
ARITHMETIC ELEMENT
li^-1 IT3TR0DUCTI0N
The Arithmetic Element has a two-fold nature: (l) it is used in the execution of a specific
group of operation codes, (2) its A, B, C and D registers are part of the V Memory. Since
the V„^ Memory is discussed in detail in Chapter 11, this chapter only briefly describes the
Y register driver logic affecting the A, B, C and D registers and instead emphasizes the
role of the Arithmetic Element in processing instructions.
The chapter proceeds by first classifying all the Arithmetic Element operation codes
according to the use they make (or do not make) of the AK, ASK and D counters. The execution
logic of each operation code in the sub-classes is then discussed. The net effect is to
bring into focus the ways in which the Arithmetic Element can process data.
The logic circuits integrated into the A, B, C and D registers are next discussed. This
includes a discussion of the shift and carry circuits and the t) counter circuit.
Since there are a large number of special purpose logic nets, these are then itemized and
discussed.
Finally all the Arithmetic Element register driver logic is tabulated and discussed.
lif-2 ARITHMETIC ELEMENT INSTRUCTION CLASSIFICATION
The computer currently has twenty-nine operation codes that make use of the Arithmetic
Element. It is convenient to classify these operation codes in terms of the use they make
of the AK, ASK and D counters.
Fig. lij--l shows the Arithmetic Element operation codes classified in this manner.
li^-2.1 AK TYPE INSTRUCTIONS. Ihe execution logic for these instructions has the following
features:
1) During the operand cycle, the Arithmetic Element register driver logic is
controlled entirely by PK or QK time levels.
2) The register transfers in the Arithmetic Element are simple, i.e., they
do not involve complex logic. For example, the only Arithmetic Element
register driver pulses involved in these instructions are those that clear,
complement, and transfer the contents of the E register into the Arithmetic
Element registers. (The complementing pulses are used only in two operation
codes, INS and ITA. )
1^-^ March I961
Fig. l4-2 shows a functional block diagram of the Arithmetic Element for AK type
instructions.
The load and store type instructions involve simple register transfers between E
and the Arithmetic Element registers (or vice versa). These instructions have the
following features:
1) During an Arithmetic Element load or store type instruction, the operand
always passes through the Exchange Element. This path is followed so that
even though the operand is stored or is to be stored in one of the
Arithmetic Element registers of the V^„ Memory, it still may be configured.
Thus in a IDA instruction it is possible to load A, with the content of
A_^ . The initial content of A is placed in the Exchange Element, configured,
and the configured operand placed back in A.
2) When a LDD instruction is executed (or for that matter any instruction
which places an operand in D), the bit placed in D. is transferred by a
parallel path into Y. . The Y bits are used in sign control only. The
programmer has no access to the Y bits.
Generally the procedure in the logical instructions INS, ITA and IMA involves
transferring Arithmetic Element data into the Exchange Element; logically processing
the data in the Exchange Element; and then, usually transferring the result back
into the Arithmetic Element. (in INS and ITA the execution logic for the instruction
does require certain complementing logic to occur in the Arithmetic Element.)
The Z flip-flops are not affected by any of the AK type instructions.
lij-2.2 AK TYPE INSTRUCTIONS. The execution logic for these instructions involves q.-ulte
different Arithmetic Element features than the AK instructions. For example:
1) In these instructions, the Arithmetic Element is "loosely" coupled to the
central computer, i.e., once the operand is transferred into the Arithmetic
Element, the Arithmetic Element time control is tijrned over to the AK
counter. While the AK type instruction is being executed, the central
computer can execute any additional instructions which do not involve the
Arithmetic Element.
2) In addition to the standard register driver logic for clearing, complementing,
etc., the AK type instructions can make use of the following "multiply step"
and "partial addition" register driver logic:
March I961 l4-5
A.
1.
a) ^ ^i.j -
-^-
— ►
A. .
A , , -
c. .
^i.(j+l)
A • T)
1
c
i-j
T) © A
A
1-J l.J
J
\-J
Miiltiply Step Logic
Partial Add Logic
3) These instructions can use the shift and carry circuits integrated into
the A and B registers.
h) These instructions can use the D register to count.
5) These instructions make functional distinctions among the Arithmetic
Element registers.
Fig. lk—3 shovs a functional block diagram of the Arithmetic Element for AK type
instructions.
In all of the AK type Instructions, an operand is brought from memory into the
Arithmetic Element before the instruction is executed. The fact that the operand
may be located in the A, B, C or D register of the V^^ Memory is not a contradiction
rr
of the above statements, but merely emphasizes the fact that the register hardware
may wear the V hat as well as the Arithmetic Element hat.
Notice that in all the AK instructions but TLY, the operand brought from the Memory
Element is placed in the D register. In the case of TLY, the operand is placed in
the A register. This means that before AK actually executes the instruction, the
only data found in non-operand registers will be that left from a previous in-
struction.
Just as the D register generally contains the instruction operand, the A register
generally "accumulates" the result of the instruction, e.g. if a series of additions
are performed, the running smi is found in A.
14-2.2.1 Z FLIP-FLOPS. The ability of A to accumulate the results of a series of
instructioiB leads to the possibility of A overflowing. In the case of
addition, overflow occurs when the accumulation exceeds the size of the
subword in which the sum or difference is accumulated. One of the
functions of the Z flip-flops is to indicate these overflows. The Z flip-
flops are also used in sign control. Only the Z flip-flops in the sign
quarters of A are used for any of these purposes. (The sign quarter is
the left most quarter of an active subword. )
lh-6 March I961
Fig. ik-k shows how the different instructions affect and make use of Z.
Z is cleared at the beginning of the four arithmetic instructions: ADD,
SUB, MUL and DIV. In the case of the other instructions, except SCale
and Normalize, Z is left in the state determined by the previous in-
struction.
In the case of the SCale and Normalize instructions involving A, the
content of Z may be shifted into A. (This will be discussed in greater
detail when the SCale and Normalize instructions are described.) Z is
used in the MULtiply and DIVide instructions for sign control. If Z. and
Y. (which remember the sign of A and D, respectively) are the same, the
product or quotient is given a positive sign; if Z and Y differ, the
product or quotient is given a negative sign. Note that Z is also used
in the DIVide instruction as an overflow indicator. (The logic for
accomplishing these two functions in the same instruction will be discussed
later in the chapter-) The other two instructions which use Z as an over-
flow indicator are ADD and SUB.
Certain Instructions always leave Z in a cleared state. These instructions
are: MULtiply, which uses Z just for sign control; and SCale and Normalize
(involving A), which can shift the contents of Z into A. The other AK type
instructions neither make use of nor affect the Z flip-flops. These
instructions are DSA, TLY, CY-, and SCB.
lij-2.3 ASK TYPE INSTEUCTIONS. The ADD, SUB and DSA instructions which make up this class
are executed by a common basic logic. Note that the B register is not used in the
ASK instructions which use AK.
lij-2.3.1 ADD AND SUB. A ONE's complement ring adder is formed in which an end
around carry occurs. E.g., suppose it is desired to perform the following
subtraction:
111 subtrahend
10 minuend
11 difference
In the computer the minuend will be complemented and the terms added, i.e.,
111 subtrahend
sign bits4
10 11 complemented minuend
11 difference
March I961 14-7
As we saw earlier in the chapter, it is possible for overflow to occur
in the addition and subtraction processes. Fig. ik-'^ summarizes the
basic overflow logic for ADDition. Note that SUBtraction is simply
addition with the minuend complemented.
The key fact is that overflow can only occur when the sign of the augend
and addend are the same. The overflow rules are as follows:
1) If the signs of the terms are positive and the sign of the sum
is positive, overflow has not occ-urred.
2) If the signs of the tenns are positive and the sign of the sum
is negative, overflow has occurred.
3) If the signs of the terms are negative and the sign of the sum
is negative, overflow has not occurred.
k) If the signs of the terms are negative, and the sign of the sum
is positive, overflow has occurred.
5) If the signs of the terms differ, then overflow can not occiir.
Another way of saying this is: "Overflow can occur in ADDition only
when the sign of the sum differs from the sign of both terms".
The computer logic for ADDition overflow is also shown in Fig. l4-5. Z
is cleared at the beginning of the instruction. A "partial sum" of the
signs of the augend and addend is then stored in Z. Note that ONE's in
the Z flip-flops indicate that the signs of the terms are similar. A
reset Z pulse is then fired which clears Z to ZERO if the sign of the
sum is the same as the sign of the ai;igend. Note that in the non -overflow
cases where this is true, Z already contains ZERO and thus the clear pulse
is not necessary.
lij--2.3.2 DSA. This instruction is very similar to the ADD instruction except that
the complete carry reqiiired in the addition process is not executed. For
this reason no overflow problems arise. Hence the Z flip-flops are left
unaffected by the instruction.
In DSA the logical sum of A and D is placed in A and the accumulated
logical product is placed in C. That is.
1^-8 March 1961
Logical Sum (or "partial add"): A © D 1^ A
Accumulated logical product (carry) : C + (A ' D; ^- C
Suppose that a DSA is executed with the following data:
Before Processing Data
10 11 D "^
110 1 A V Operand Data
C J
The DSA instruction leaves the D register unaltered and the A and
C with the following results:
After Processing Data
Eesult
14-2.4 ASK TYPE INSTRUCTIONS. These instructions are characterized by an operation or
series of operations which (somewhere in the execution of the instruction) are
repeated a finite number of times. The usual function of the ASK counter is to
keep track of the number of iterations. Because of this iterative characteristic^
the execution of the instruction generally requires considerably more than the
usual instruction time.
14-2.5 COUNT IN D TYPE INSTRUCTIONS. This subclass is made up of the MUL and DIV in-
struction. In these instructions all the Arithmetic Element registers are used as
well as the Y and Z flip-flops.
14-2.5.1 MULTIPLICATION. In this instruction, the multiplicand, which is the
operand from memory, is loaded into D. The multiplier is the data left
in A from a previous instruction.
Early in the execution of the instruction, the multiplier is transferred
from A into B and A is then cleared. There then begins an iteration of
"partial add - multiply step" cycles. It is the function of the ASK
counter to see that the correct number of iterations occur. The actual
number depends on the size of the subwords used, i.e., on the fracture.
March I961 l4-9
The partial add performs the following logic:
Partial Add
A. . • D
i-J
A. . e D. . — 3-
i-J
The before and after states of the Arithmetic Element registers during
partial add might typically be as follows:
Before PAD
D
1111
c
10
A
11
111
\
PAD conditional on right
most bit being 1
After PAD
D
mill
C
|0 1 1 1|
A
1 1 1 1
The multiply step pulse processes the carries in C and shifts the running
sum in AB one bit to the right. This is done by a single pulse. The
logic involved in this operation is as follows:
Multiply Step
\<J^-^/ -L.J -L.J.
i.(j+l)
1-J
h.l -^— ^ \.9
i.(j+l)
i-j
lif-lO
March I961
The effect on the Arithmetic Element registers of folloving the PAD
described above with an MS (miiLtiply step) is as follows:
After MS
D
1
1
1
1
1
1
|o
1
This process is iterated the correct nimber of times and then the carries
I CRY
left in C are absorbed into the A register by a carry pulse ( I ► A).
Note that this complete carry is performed only once during the execution
of the Multiply instruction. At the end of the instruction, AB contains
the product. The major half of the product (most significant bits) is in
A and the minor half of the product (least significant bits) is in B.
The fracture (f ) specified in the MULtiply instruction determines the AB
subword length. The AB possibilities are shown in the table on Fig. li4--3'
For example, if an f (l8,l8) fracture is specified, two independent
products will be formed if there is more than one active subword ' involved.
A 36 bit product will be contained in A, - A - B, - B with A, the sign
quarter. At the same time, a 36 bit product will be formed in Ap - A_^ -
B_ - B with Ap the sign quarter. However, in the case of f (27,9), the
9 bit subword product will not be correctly generated.* The f, (9,9,9,9)
form must be used to obtain the correct product in the right quarter.
lij--2.5.2 DIVI SION. In this instruction, the divisor, which is the operand, is
loaded into D. The dividend is the data left in AB from a previous
instruction. The major half of the dividend is located in A and the
minor half of the dividend is located in B. The dividend must have the
same form as the product left by a MUL.
The C register is used to keep track of the carries involved in the
partial adds, just as in Multiplication.
At the end of the DIVide instruction, the A register contains the signed
quotient and the B register contains the signed remainder. The sign logic
is based on the following simple algebra:
* At the moment the ASK counter can be used for only one subword length at a time. A modification
will be made so that ASK can count both for 27 and 9 hit subwords simultaneously.
March I961 l4-ll
DIVIDEND =. QUOTIENT + REMAINDER
DIVISOR
DIVISOR
AB = A + B
D"
The sign rules are:
1) The sign of the quotient is positive if the signs of the
dividend and divisor are the same^ and negative if these
signs are different.
2) The remainder alvays has the same sign as the dividend.
The mechanics of the DIVide instruction will he explained by examining
the example below. The example has been chosen because it produces an
overflow. Let the operand in D and data in AB be the following:
D
10
1
AB
10
1
000 000 010
If AB is positive, AB is complemented. (The signs of D and AB are
remembered by Y and Z respectively.) Thus,
10 OOP ooTj
ASK = 170
Z AB 101 111 110
111 111 101
Because of the f, fracture, ASK is preset to 170. ASK now counts out
the "partial add - carry" loops as they are executed.
The first PAD pulse leaves the A register looking as follows :
111 111 111
If the sign of A now differs from that of D, D is left unchanged and
AB is shifted one bit to the left by the CRY pulse. This leaves the
registers as follows:
1J+-12
March I961
Piffl
D
10
1
A
111
111
111
ffl
111
111
111
ASK = 171
111 111 Oil
This process is repeated. Note that in the next iteration^ the sign of
A is the same as the sign of D, therefore D is complemented. This is
done so that the PAD pulse always adds terms of unlike signs, i.e.;, a
subtraction always takes place. Thus,
ASK = 172
i 1 1
111
1 1 1
j 1
1
1 1
p 1 i
Again the process is repeated. In the next partial add, ^. g i^
"carried" into A "because a final "fix up" pad is executed on the hasis
of the sign hit in A being ZERO (i.e., positive). Thus,
D
1 1 1
111
1 1 1
A
1111
111
iii|
AB
Mil
111
111
ASK = 002
100 000 000
A and B are now interchanged, so that the quotient is now in A and the
remainder is in B.
AB 100 000 000
111 111 111
Up to this point both Y and Z have been in the ZERO state. Several
things now occur simultaneously:
1) Since Z is ZERO, B is complemented.
2) Since Z = Y, A is not complemented.
3) Since A is ONE, Z is set to OKE (indicating an overflow)
i.9
Thus,
^ S ^ I 1 0"0l I 0~0~ |
March I961 1^-13
Note that since Z indicates an overflov, A does not contain the right
quotient . However, the right quotient can be obtained by following the
Divide instruction with a Normalize instruction.
lh-2.6 COUNT IN D TYPE INSTRUCTIONS
lk-2.6.1 SCA, SCB, SAB, CYA, CYB AND CAB. SCaling and CYcling are similar type
instructions. SCaling effectively multiplies the data by a positive
or negative power of 2 while preserving the significance of the sign
bit. CYcling simply rotates the data (including the sign bit) left or
right within the subword. In both SCale and CYcle type instructions,
the sign quarters of the operand in D prescribe the number of shifts to
occur.
Fig. lk-6 shows an example of a SCale AB instruction (SAB) in which an
f (18,18) fracture was specified. It is assumed that one of the sub-
words in the operand has a negative sign and that the other subword has
a positive sign.
Two cases are illustrated in Fig. lk-6. In case 1, it is assumed that
overflow indicators Z and Z, were left in a ZERO state by the previous
instruction. Case 2 assumes that the same overflow indicators were
left in the ONE state by the previous instruction, i.e., that an over-
flow occurred in these instructions .
The following events take place in the SAB instruction. The sign
quarter of the left subword in D is complemented. This occurs because
the original sign bit of the operand, now stored in Yi , is positive
(zero). The sign quarter of the right subword in D is not complemented,
since the operand is already negative (ONE). The operand in D,
specifies the number of shifts that will occur in the data in the
associated AB subword Aj^ - A - B^ - B . The fact that Y^ is ZERO
means that the data will be shifted to the left. Similarly the operand
in D specifies the number of shifts that will occur in the data in AB
subword A - A - B - B . The fact that Y is OWE means that the data
will be shifted to the right.
First consider Case 1. Here the overflow bits in Z are both ZERO. The
logic of the SCale instruction requires that the sign bit be left un-
changed, therefore no shift into the sign bit occurs. Consider now
the left subword. If the sign bit is ZERO, shifting should fill up the
right end of the subword with ZEROS. If the sign bit is ONE, shifting
should fill up the right end of the subword with ONES. Shifting the
sign bit (A, ) into the right end (B ) accomplishes just this result.
lij-lU March I961
In the case of the right sutvord^ shifting right should fill up the
left end of the suhword with ZEROS, if the sign hit is ZERO and OKES if
the sign bit is 1. Shifting the sign bit (A ) into the left end
(a n) accomplishes just this result.
Now consider Case 2. Here the overflow indicators Z, and Z have
both been left set to OWE by the previous instruction, i.e., an over-
flow has occurred. The overflow has caused an error in the sign, there-
fore the sign must be complemented before the data is shifted. The
mechanics of the instruction are then the same as in Case 1. The ONES
in Z, and Z are cleared to ZERO by the SAB instruction, since the
overflow is taken care of by the instruction.
Fig. lU-7 shows an example of a CYcle AE instraction (CAB) in which the
same operand, data, fracture and overflow conditions are used as were
used in the SAB example. The example illustrates the basic differences
between the two types of instructions .
In the case of CAB, the entire subword is shifted in a closed ring.
The sign bits are given no special treatment. In Case 2, in which the
overflow indicators have been set to OWE by a previous instruction,
the CAB instruction does not affect and is not affected by the state of
the Z flip-flops.
In both SCale and CYcle instruction ASK performs no useful function
during the execution of the instructions. It simply is indexed once
each time a shift occurs . The number of shifts which take place are
determined by the D counter.
lk-2.6.2 NOA AND NAB. These instructions take the data left in A or AB and
multiply it by that positive or negative power of 2 required to make
the value of the data lie between l/2 and 1. The sign quarter of D
counts the number of shifts to the left or right required to do this .
Effectively, the number of shifts to the left required is subtracted
from the sign quarter of the operand brought from memory and placed in
D.
In this instruction ASK prevents unlimited shifting from occurring when
A or AB contains all ZEROS or all ONES.
Overflows are handled exactly as they were in the SAB instruction
previously described.
March I961 lU-15
lU-2.6.3 TLY. This instruction is unique in that the operand from memory is
placed in the A register. Neither the B or C register is used in this
instruction.
In this instruction the data placed in A is completely rotated once and
left in its original position. The ASK coimter is used to count the
number of shifts required to completely "cycle" the subwords . The D
counter "tallies" or counts the number of OWES that are contained in
the data. The number of ONES is added to the contents of the sign
quarter in D left from the previous instruction. The TLY instruction
has no effect on the overflow indicators .
Fig. lU-8 summarizes the use of the ASK and D counters for ASK type
instruction.
Fig. lU-9 summarizes the function of the Arithmetic Element registers
and the Y and Z flip-flops for all the AK instructions .
AE AF
ll^-2.T OPR ("AOP") VS OPE ARITHMETIC ELEMENT INSTRUCTIONS. All of the basic AK
instructions discussed so far can be specified by the AOP instruction. This
instruction has several characteristics:
1) The Y bits of the N register are used to specify the instruction and
its configuration. The Y bits do this by setting the state of the AKIE
ajid AKIR^_ registers directly with no intervening decoding.
CF
2) In this instruction there is no memory operand or operand cycle. The
data in what would ordinarily be the Arithmetic Element operand register
is the data left there from a previous instruction.
3) Because the part of an Arithmetic Element instruction in which an
operand is taken from memory^ configured in the Exchange Element and
then loaded into an Arithmetic Element register is absent in the AOP
instruction, the effects of configuration specification are different.
Fig. 1^1-10 shows a comparison of an AOP and AOP instruction.
The AOP instruction is a CYA in which only quarter 2 of an f, (36) fracture is
specified active. Similarly, the AOP instruction is used to specify a cycle A
in which quarter 2 of an f fracture is active.
Consider first the CYA instruction. The sign bit in quarter 2 of the operand
from memory is negative. This means that after the sign is extended in the
•cry'rri APrp
Exchange Element, quarters 1, 3 and h will contain ONES. The OKIE i levels
1I+-I6 March I961
generated in the Program Element and used in the Exchange Element for sign
extension are also used by the Arithmetic Element to determine which quarters
EXT ACT ^ _EXT ACT,
are active. For example;, the fact that QKIR 3^ QKIR ^ and
■crym APrp
OKIE 1 levels were generated to extend the sign into the third, fourth
and first quarter means that the a , a, and a levels will be generated by
AKIR • This will activate the 3rd;, llth and 1st quarters of the Arithmetic
CF
Element. Note that because of this all the quarters of the Arithmetic Element
are active . Any shift that occurs because of the CYA instruction will cycle a
36 bit word in a closed ring.
In an f (36) fracture the contents of quarter k of D (i.e., the sign quarter)
will determine how many shifts are to take place. Sign extension has filled
quarter k with OWES, however. This means that no shifts will occur in the
instruction as specified.
Now consider the AGP equivalent of the AGP instruction. Assume that the same
operand brought from memory in the AGP instruction previously discussed, is, in
the present instance, left in D from a previous instruction.
Assume that the Y bits of the W register specify an f^ fracture and quarter 2
is active. This means that AKIE _ vill generate an f^ level and an a^ level.
Coupling units in the Arithmetic Element connect the various quarters of A and
B on the basis of Instruction, activity and fracture. In the present case, the
fact that f and a in a cycle A to the right instruction (assume that the sign
bit (Y, = D, ) is a GNE) are specified means that A ^ will be coupled to ^^ „•
However, no shifting will occur into A , A , and A^. If A ^ contains a ZERO
and D, specifies more than 9 shifts, A will fill up with ZEROS.
This example suggests the main differences between AOP and AOP instructions.
lk-3 ARITHMETIC ELEMENT REGISTER OPERATIONS
This section will discuss the various types of register transfers that can occur in the
Arithmetic Element. The basic transfers, which are finite in number, are used to
execute all the Arithmetic Element instructions .
1^1-3.1 STANDARD TRANSFERS. Fig. ^-11 shows the standard register operations common to
A, B, C and D. These operations are:
l^A
(B, C and D and Y)
LC^ A
(B, C and D)
-2-^A
(B, C and D and Y)
March 1961 ik-YJ
The execution of certain instructions requires that the contents of A be jammed
into B (e.g.j, in the MULtiply instruction) , or that the contents of A and B he
interchanged in a jam transfer (e.g.; in the DIVide instruction). Fig. lU-12
shows these jam transfers.
1^4-3.2 SPECIAL LOGICAL TRANSFERS. Fig. li|-13 and l^l- show two special logical transfer
circuits in the Arithmetic Element.
I PAD
The transfers shown in Fig. 1U-I3 are initiated hy a "partial add" pulse ( I ► )
This pulse complements A. . if the corresponding D. . bit is a ONE. This is the
"exclusive OR" transfer used to perform a partial add. At the same time^ the
PAD pulse sets C. .to ONE, if the corresponding A and C bits are OWES. This is
a carry operation based on accumulating in C the logical product of A and D.
Note that if C were in the ONE state when a ONE was "carried" into it during
a partial addition, the logic of the arithmetic would break down. Later we shall
see that, except during DSA, C . .is always in the ZERO state when a ONE is
carried into it due to the over-all Instruction logic .
The transfers shown in Fig. 1^-1^1- are initiated by a "Multiply Step" pulse. The
Multiply Step operation really does several things at the same time. Basically
the operation shifts the content of A and performs a partial addition of the
contents of C and A.
The example below illustrates the main features of the Multiply Step operation:
A. / .^T% © C. . — j— ». A. .
Before MS (After PAD) After MS (Before PAD)
110 G
oil
— Sign Bit
OOlllB. ^ A 0101
1.9
A. r ■_.-, ^ ^-^*- C. .
i-(.J+l) i-J
0110 C 0010
/
110 A
Since both these transfers occur at the same time, the net effect is as follows:
A. / .^.\ ® C. . ► A. .
A. , .^^^ —5 ► C. .
1^-18 March I961
The following truth table shows all the possihle effects of the Multiply Step
operation on the A and C register:
Before MS
After MS
^•(j-1)
■c .
i"J
A .
i-J
c .
i-J
1
1
1
1
1
1
1
Note that A and C are never hoth left in the ONE state by the Multiply
Step operation.
From the arithmetic point of view, the partial addition logic adds the contents
of A and D bitwise, leaving the carries in the C register. No inter-bit logic
occurs in this partial addition. The Multiply Step operation performs a partial
addition between the content of the C register (i.e., the carries left in the C
register) and the content of the A register. The carries from this partial
addition are placed in the C register and the content of the A register are
shifted to the right.
ll|_3.3 D EEGISTER COUNTER. Fig. 1^4-15 shows the operation of the D register coimter.
As pointed out earlier, the D register is always preset to a negative mmiber and
then counts up to a negative zero, i.e., all ONES. The counter logic says that
D will not be complemented unless all the bits to the right of D (i.e.,
i-j ^ ^
D the rough D , . ^ are ONES ,
i-JL I'lJ-j-J
1I+-3.I+ SHIFTING OPEEATION. Fig. lk-l6 shows the circuitry arrangement for shifting left
and right. The A register shift circuits are shown in Fig. 1^4-16 (the B register
shift circuits are similar in arrangement).
The shift circuits must have sufficient flexibility to accommodate all the possible
fractures and instructions. To provide this flexibility, the quarters are designed
with "shift coupling units" at the ends. The shift operation involves a bit-wise
jam transfer.
Note that the shift right circuitry has a coupling unit at the left end. This
unit determines what bit (if any) will have its content shifted into A^_^ when
the l^™»- A pulse is fired. There are eight possible transfer paths into A^_^:
A — 3— ► A. (K = 1, 2, 3, ^) and (in AB type coupling) B^.^ — 3—^ \,^
(K = 1, 2, 3, h). Which of the eight possibilities used is determined by the
fracture and the instruction. The coupling unit contains the necessary logical
circuitry for making the decision.
March I961
Ik -19
The shift left circuitry is similar to the shift right circuitry vith one slight
variation. In some instructions, e.g., SCA, and fractures, A. _q is the sign bit.
For these instructions the instruction logic may not shift A o into A ^ . For
this reason, the shift left circuitry has two Shift Left Coupling Units: one at
the right end of the quarter and the other between the A n and A. ^ bits.
i-o i*y
1^-3.5 CARRYING OPERATIOK. Fig, 1I1-I7 shows a logical block diagram and transistor block
schematic of the A register carry scheme.
First consider the logic of the carry scheme. The right end of the carry out in
the quarter is driven by a Carry Coupling Unit. This coupling unit has a similar
f ■unction to the shift coupling unit described above . It determines what data
will be carried into (or through) the quarter. The carry inputs are the D. _
states of each quarter and the "carry outs" (CYO.) of other appropriate quarters.
The selection logic is based on the instruction (DIV or DIV) and the fracture.
The logic can be broken down into two parts: the bitwise carry logic within a
quarter, and the logic involved in carrying between quarters .
Consider a typical stage for i 5^ 1. The carry into this stage (CYI. .) is
identically the same as the carry out of the previous stage (CYO. / •_-i"\)-
This carry circuit is used to propagate a "complete carry" through the A register.
For example, in MULtiplication a number of partial adds and multiply steps is
followed by a final complete carry. At any one stage in the execution of the
MULtiplication, the A register contains the current accumulation of partial
additions and the C register contains the current acc-umulation of partial
carries . In the complete carry, the carry bits in C must be correctly brought
1 CRY
down into the A register. The ' ► pulse does this.
If a carry level into the i-j stage (CYI.. .) is present, it will complement
A. . when the' ► A pulse is fired.
i"J
A carry out of the i'j stage will occur whenever C. _ ., or A. _ . and a carry in
(CYI .), occurs.
A carry into a quarter (CYI.) will occur whenever the carry coupling logic is
satisfied. The i.l stage will then treat CYI. as a normal CYI. . is treated.
1 1' J •
A carry out of the quarter (CYG.) will occur if either a carry into the quarter
1 1
occurs (CYI ) and the quarter contains all ONES (A.), or if a carry out of the
i 1
i.9 stage occurs. Note that CYO..Q will not be generated unless the quarter does
not contain all ONES (A.). This logic allows the carry to bypass the quarter if
it is already loaded with ONES, This saves the time required to propagate the
carry through the quarter.
li+-20 March I961
ik-k ARITHMETIC ELEMENT LEVEL LOGIC
This section vill discuss the interpretation of the control information found in the
AKIE and AKIE registers. It -will also discuss in detail some of the special level
logic nets found in the Arithmetic Element. For example^ the logic details of the shift
and carry circuits will he examined.
lij-i]-.l AKIE AM) AKIE REGISTEES . The Arithmetic Element receives instruction control
OP CF
commands for AK type instructions from the AKIE^„ and AKIE registers . These
registers are actually located in the Program Element. Chapter 12 descrihes how
the AKIE and AKIE registers are set up. This chapter discusses the decoc
OP CF
of these registers. Note that AK type instructions which use the Arithmetic
Element are controlle
cussed in Chapter 12,
the AKIE and AKIE registers are set up. This chapter discusses the decoding
OP CF
; registers. I
Element are controlled hy OKIE and OKIE • These two registers are also dis-
XX
li^-i^-.l.l AKIE DECODING. The AKIE register is decoded into AKIE levels hy
1st level decoders. Fig. 1U-I8 shows the names of the decoded lines.
Fig. 1^-19 shows how OP decoders in turn comhine the outputs of the 1st
DIV
level decoders to generate OP code lines. For example^ AKIE is
7X X7
generated hy a net that ANDs AKIE and AKIE . Note that not all the
Arithmetic Element instructions are decoded in this way, e.g.;, SUB (77)
is decoded, hut ADD (67) is not.
Still another set of levels is generated in the AKIE decoding process
hy class decoder nets. These class levels group the Arithmetic Element
instructions hy common characteristics. For example, one level can he
used to indicate a class of instructions in which shifting takes place.
Fig. 1^1-20 tabulates the logic used to generate the class levels. The
significance of these levels will hecome apparent when the logic which
uses them is discussed. For reference purposes, a hrief description of
each class level is given helow:
err
AKIE - is generated when any one of the CYcle or SCale
instructions is specified. These instructions shift 'data
in A, B or AB as specified hy the sign quarters of the
operand in D.
OTTA ^'FTR SH
AKIE AND AKIE - are hoth subclasses of AKIE . The
necessary condition for their generation is that shifting
occur in register A or B, respectively. Note that if
either CAB or SAB is specified, hoth AKIE , AKIE and
cirp
AKIE are generated.
March I961 lij-21
CY
AKIR - Implies an instruction in which data is cycled in a closed
ring. The form of the closed ring is determined by the specific
instruction and the fracture specified. The instructions which
cycle data are the CYcle instructions and the TLY and DIV
instructions .
AB
AKIR - implies an Instruction in which A and B are coupled. In
certain instructions the suhwords of A are extended by joining
them to the corresponding subwords in B. In this way an AB sub-
word is formed. This occurs in the CAB, NAB and SAB instructions,
as well as in the DIV and MUL instructions .
A+B , AB,
AKIE (= AKIR ) - self explanatory.
PY • AB
AKIR - is an example of class levels being combined to form
a new class level. This level is generated by those instructions
which cycle data from A into B (or B into A) in a closed ring.
The instructions that do this are CAB and DIV.
AKIR
CY • (A+B) _ ^^ generated by the CYA, CYB and TLY instructions.
In these instructions data is cycled in register A or in register
B, but not in AB.
2N
AKIR - controls allowable shifting. Earlier in the chapter
(Fig. lU-8), we saw that ASK is used in the CYcle, SCale, Normalize
and TLY instruction to prevent excess shifting from occurring. In
the case of CAB, MB and SAB, ASK limits the shifting to
(approximately) twice the subword length specified by the fracture.
2N
AKIR is generated in these Instructions to indicate the double
length shift allowed.
AKIR (= AKIR ) - self explanatory.
AKIR - is generated by the two Normalize instructions, i.e.,
NOA and NAB.
AKIR - is generated by either the ADD or SUB instruction. Note
" SUB _ADD
that when SUB is specified, both AKIR and AKIR are generated,
ADD
but that when ADD is specified only AKIR is generated.
Of^AT OCSAL
AKIR - is used in the OCSAL alarm logic. The AKIR level
is generated when AKIR specifies an undefined Arithmetic Element
instinction. All the Arithmetic Element instructions are in the
60 's and 70' s, but 63 and 73 are not defined. Note that this
level includes AK^, as a factor.
lij--22 March I961
AOP
AKIR - is generated whenever an undefined AOP instruction is
specified. Note that currently the defined AOP instructions are
limited to the Arithmetic Element instructions^ hence the same
OCSAL „ _AOP.
logic that generates AKIR also generates AKIR
lij-l4-.1.2 AKIR-i-rn DECODING. The AKIR register is decoded to generate fracture
CF OF
(f) and activity (a) levels. Bits AKIR„_ determine the activity,
and hits AKIR„ determine the fracture. The table on Fig. lij-21
'^9-8
shows the AKIR decoding. Note that a quarter is activated hy an a.
CF -| 1
level and that the a level is in turn generated hy an associated
^
AKIR^^ level .
CF
J
Fracture decoders use the a's and f 's as inputs to generate Rom.an
numeral levels. The unsubscripted Roman numerals (RN) indicate the
sign quarter of a subword which contains at least one active quarter.
For example, II indicates that quarter 2 is a sign quarter and that it
is part of a subword which is at least partially active.
The subscripted Roman numerals (RN.) indicate that the i-th quarter is
active under a certain special condition. This condition is that the
i-th quarter is part of a subword whose sign quarter is given by the
Roman numeral. For example, IV indicates that quarter 1 is active and
is part of a subword which has quarter k as its sign quarter.
A pictorial representation of these Roman numeral levels is shown in
Fig. 1^-21. The conditions for generating these levels are:
Roman Numeral I. The only occasion when quarter 1 is the leftmost
quarter of a subword which contains at least one active quarter is
when quarter 1 itself is the subword. Thus, I = l3_- (Note this
same argument makes III = III • ) I is generated in both the f
(27,9) and f, {9}9}9}9) fractures when quarter 1 is active
Roman Numeral II. A threefold possibility exists: either the
first quarter is active and there is an f (l8,l8) fracture, or
the second quarter is active and there is an f (l8,l8) or f^
i9)9>9>9) fracture.
Roman Numeral III and IV . The logic here is similar to that
described for I and II. Note that IV^^ = a^.
March I961 1^-23
ll+-i^-.2 ALL ZEROS (A°), ALL ONES {a[) LEVEL LOGIC. The logic generating the A° and A"^
11 i i
levels is shown in Fig. 1^-22. These levels indicate that the quarters are
filled with all ZEROS (or all OWES). A. and A. are used in the carry and jump
logic .
ll+-i]-.3 SIGMA (c7-) LEVEL LOGIC. ^ = A. „ implies sigma (a-). Fig. 1^1-23 shows the
explicit logic generating the sigma (3~) level. This level is used in the
Normalizing instructions to indicate that A. = A. „ and that consequently the
normalization process is not yet finished.
ik-k.k SHIFT COUPLING UNITS. These \mits are logic nets which determine how the quarters
of A and B are coupled together during shift instructions. In (A + B) type
instructions the quarters of A are always coupled to other quarters of A, and
similarly the quarters of B are always coupled to other quarters of B. In AB
type instructions cross coupling between the registers can occur.
Fig. 1^-24 shows the logic that relates the inputs and outputs of the Shift
Coupling Units shown on Fig. 1^4-16. Fig. li4--25 shows the corresponding shift
coupling logic for register B.
For the moment consider Fig. l)+-2^. Note that all of the shift right logic
involves inter-quarter shifting. If the instruction is an (A+B) type, A. ,
will be shifted into A ^ , . The specific bits shifted will depend on the
i.9 s
fracture. If the instruction is an AB type, B. ^ , will be shifted into A .
•^■^ i.l's 1.9's
Again the specific bits shifted will depend on the fracture. Regardless of
which type instruction is involved, i.e., (A+B) or (AB), certain quarters of A
will be coupled to other quarters of A by the last term in the shift coupling
logic .
The logical format for shifting in B is similar and shown in Fig. lU-25.
Fig. 1^4-26 shows a specific example of shift right coupling for both an (AB) type
instruction and an (A+B) type instruction that have an fp fracture. Note that
in both instructions the same logic couples A, to A and A to A , In the (AB)
type instruction, the sign quarters of the subwords are A, and A , respectively.
No shift into A^ q °^ -^o n "wiH occur unless the instruction is a shifting
instruction which ignores the sign bit, i.e., CY • AB = CAB + DIV. Since B, and
B_ are not sign quarters, it is only necessary that the instruction be an AB
type, i.e., (CAB + NAB + SA^) + (MUL + DIV) in order that A be coupled to
B, and A be coupled to B
Note in Figs. li+-2^ and lU-25 that the fractures in the column "independent of
AB/(A+B)" are always the complement of the fractures in the "AB and A+B" columns.
1^-24 March I961
The inter-quarter shift left logic shown on Fig. lij-2ij- and li^-25 is similar in
format to the shift right logic with one important exception. Since in a shift
left instruction we are always shifting information into i.l, there are no sign
hit considerations. This means that the shift is independent of whether the
instruction is or is not of the CY type and depends only on whether it is of the
(AB) or (A+B) type.
In the case of shift left^ coupling imits are also required hetween the i.8 and
i.9 hits^ i.e., intra-register coupling exists. If a CY type instruction is
involved, no sign bit consideration is involved and i.8 is always coupled to i.9'
If the fracture is f (36) or f (l8,l8), 1.8 will always he coupled to I.9,
since in either fracture I.9 is not the sign bit. Similar logic is involved for
coupling into 2-9, 3.9 and ^.9 during a shift left. Note that ^.9 is always a
sign bit regardless of the fracture.
If an AB instruction is involved, B. ^ will never be a sign quarter, therefore
1.9
B . o is alwavs shifted into B. ^ on a shift left instruction.
1 .0 '^— 1.9
In passing, it might be mentioned that the speed of the coupling logic nets them-
selves becomes critical if the shifting rate approaches 5 megacycles .
llj-U.5 CARRY COUPLING UNITS. Fig. ih-ZJ shows the logic that relates the inputs and
outputs of the Carry Coupling Units shown on Fig. ih-YJ . Note that CYI^
represents a carry into the i-th quarter, while CYO. represents a carry out of
the i-th quarter.
For dTv type instructions, the carries are propagated in a ring whose constituents
are determined by the fracture. For example, suppose an f^ fracture is specified
for a DIV type instruction. The quarter wise carry picture would then look as
shown in Fig. lij-28(a).
In the Divide instruction a 2's complement-like arithmetic is used. The logic of
this arithmetic requires that a 1 be added if the sign bit in D is negative.
This is shown in Fig. li|-28(b). The inter-quarter carry logic is the same for
both DIV and DIV instructions . Only the end around carry differs for these two
cases.
Note that the carry logic format shown on Fig. 1^1-27 is very similar to the shift
logic format shown on Fig. 1^-2^)- and 1J+-25.
Ik-h.G AEJ LEVEL LOGIC. AEJ is a level which indicates whether a jump is to be made,
based on the contents of the Arithmetic Element. It can be generated during a
JPA, JNA or JOV instruction. The function of AEJ for each of these instructions
is as follows :
March I961 l4-25
JPA - If some active subword contains a positive non-zero (arithmetically)
number ;, AEJ will be generated and cause the output of the XA (X Adder) to be
copied into P.
JUA - If some active subword contains a negative non-zero (arithmetically)
number^ AEJ will be generated and cause the output of the XA to be copied
into P.
JOV - If some active subword has a Z flip-flop in the sign digit position
set to OWE, AEJ will be generated and cause the output of the XA (X Adder)
to be copied into P,
Fig. 1^1-29 shows the logic generating the AEJ level. Note that the presence of
any one of the terms is sufficient to generate AEJ.
As an illustrative example, the conditions for causing a jump based on the con-
JPA
tents of A will be discussed. If a JPA is executed, PKIE will be generated.
L" yi I' APT"
OKIE 2 indicates that the quarter 2 of the Arithmetic Element is active,
while A indicates that the sign bit is positive. Note that A is the sign
2.9 2 .y
bit in an f^ (l8,l8) or f, (9,9,9,9) fracture. The additional factor in the term
2 4
on Fig. 1^-29 insures that the active subword contains a non-zero number. Note
that in an f (l8,l8) fracture it is sufficient that quarter one not contain all
To f
ONES or all ZEROS , i.e., A • A^ • QKIR 2; while it is sufficient in an f^
(l8,l8)_or f^ (9;.9;.9;>9) fracture that quarter 2 not contain all ONES or all ZEROS,
i.e., A^ • A^ • QKIR^2 ^k.
The logic for JNA is the same, except that Ap must be in the ONE state.
The JOV logic is also similar. Z^ is in a sign quarter in an f^ (27,9) or fj^ ■
(9j9:.9;9) fracture. Z^ is in a sign quarter in an f^ (l8,l8) or f^ (9^9^9^9)
fracture, etc. Note that Z, is always in a sign quarter regardless of the
fracture .
ll+_l+.7 LH— ♦ AEP LEVEL LOGIC. ' ♦■ AEP is used to clear to ZERO the AEP (Arithmetic
, .
Element Predict) interlock flip-flop. (See Chapter 10.) AEP indicates that the
Arithmetic Element will soon be available for use by another Arithmetic Element
instruction. For each Arithmetic Element instruction and configuration an event,
before the completion of the AK cycle, is chosen to generate the ' ♦ AEP level.
The AEP level effectively predicts the maximum time required for the balance of
the AK cycle. This maximum of the maximum times is 2.8 microseconds and occurs
during an ADD instruction with an fT fracture . During other Instructions and
with other configuration the time can be less .
14-26 March I961
Fig. 1^-30 gives the anticipatory logic for generating the ' ♦ AEP level. The
first term in this logic is concerned with the Normalize instructions . In these
instructions the data in the suhword is shifted until the value of the data lies
hetween l/2 and 1, I.e., the left-most hits in the sign quarter must he 01 or 10.
If the sign quarter contains neither all ZEROS nor all OKES, the greatest number
of shifts that can occur before the data is normalized is eight. For example,
suppose the suhword contains the following data:
SIGN QUARTER
jllllllllO ~| ~xxxxxxxxx]
If a Normalize instruction is executed, after seven shifts the data will he
normalized, i.e., the sign quarter will look as follows:
lOXXXXXXX
The example just given was a "worst condition" case. The data to he normalized
might have been:
llOXXXXXX
In this case only one shift is required to normalize the data.
Note that if the sign quarter is quarter 1, then a Roman numeral I will be
generated, and it is necessary to know only that this quarter does not contain
all ZEROS or all ONES to know that a maximum of seven shifts will occur before
the data is normalized.
In the case where the subword contains the following data,
SIGN QUARTER
111111111 lllllOXX X
I
six shifts occur before the ' ♦AEP level is generated. AEP then indicates
that a maxiimum of seven additional shifts will follow before the data is fully
normalized.
I
The second term in the ' ♦ AEP logic is concerned with the SH instructions
(i.e., CYcle and SCale). Since the D counter always coimts up to zero from some
negative value in these instructions, it is always possible to know how long the
count will take to complete from an arbitrary but predetermined counter state .
IAD is used as the reference event in the count. LAD. anticipates how long it
will take to complete the count in the i-th quarter of D. If a Roman numeral II
is generated, we are interested in the LAD- level, etc. The logic here is very
similar to that for the NOR instructions.
March I961 1^-27
The third term in the ' ♦AEP logic is associated with the ADD, SUB and DSA
instructions. In this case, the balance of the AK instruction time depends only
on the reference AK state .
In the Divide instruction, it is necessary to know both the state of the AK
counter and the ASK counter to predict the balance of the AK instruction time.
The fifth term is concerned with the case where the ASK counter overrides the
D counter. This is the case where some active subword contains all ZEROS or all
ONES. In the Normalize instructions, after a certain number of shift counts
have occurred, AEP*^ will indicate that there are at least no more than 6
additional shifts to occur. In the TLY instruction, after a certain number of
shifts counts have occurred, AEP will indicate that there are exactly 6
additional shifts to occur.
The MUL term logic is similar to the DIV term logic.
Finally, in the case of an undefined AOP instinaction, a finite time exists
between the generation of the AKIE level and the completion of the AK cycle.
AOP
Note that AKIE includes an AK time level, i.e..
AKIE^°^ = AK^_^ ((AKIR^^ • AKIeJ^) + AKIR^^)
AEITHMETIC ELEMENT REGISTER DEIVER LOGIC
The remainder of the chapter will discuss the specific register driver pulses found in
the Arithmetic Element and the logic generating these pulses.
All of these register driver pulses are tabulated on Fig. lli-31- This figure shows the
various logic and counter time levels that are found in the register driver logic. For
example, the sigma (o-) levels are found in both the D counter register driver logic and
in the shift register driver logic.
Fig. 1^1-32 tabulates all the pulse gate logic. In some cases the gating logic is quite
simple, in other cases it is quite complex, e.g., the gating logic for the Z flip-flops.
Once the logic generating the register driver pulse is known and the pulse gating logic
is known a comprehensive picture of the register operation can be established.
1^-5 1 ^71 + 1 — ►!) ED LOGIC. (See Fig. lH-33). Counting will occur in the
i I i
quarter of D corresponding to the sign quarter of the subword in A. The Roman
numerals indicate the sign qmrters . The FD. levels indicate when the D counter
has counted up to zero. The count pulses are then inhibited by the FD^ levels.
ll|.-28 March I961
In the SH type instructions (CYcle and SCale)^ counting is initiated at AK^, ^•
Overflow control occurs at AK^ ^ and then AK counts on to MT , . The major
portion of the counting in D then occurs in AK , •
In the TLY instruction^ D counts the OWES that appear in the sign hit of A at
AK as the subword is cycled (rotated).
During the Normalize instructions^ D coxmts^ i.e., continues to normalize, as
long as A. = A. q. This equality is indicated hy the ^ (sigma) levels.
Note that ASK can override the D counters hy forcing AK into a new time state
even though the D counter register driver logic is not satisfied. D then. stops
counting, even though the FD. levels are not generated.
14-5.2 A REGISTER SHIFT RD LOGIC. (See Fig. ik-^k) . During a TLY instruction, shifting
to the right occurs in all the active quarters of A. The shift decision is
independent of any fracture considerations.
During a Normalize type instruction, the active quarters of a subword are shifted
to the right if the Z flip-flop in the sign quarter of the subword indicates an
overflow. Note that there are three possibilities that can cause a shift right
to occur in A.
Z ■ I Quarter 1 is active and is also the sign quarter. Z • I
indicates that quarter 1 is part of a subword in which an
overflow condition exists .
Z • II Quarter 1 is active and the sign quarter is quarter 2. 2. • II
indicates that quarter 1 is part of a subword in which an over-
flow condition exists .
Z, • IV Quarter 1 is active and the sign quarter is in quarter h.
1
Z, 'IV indicates that quarter 1 is part of a subword in which
an overflow condition exists .
The shift right logic for the other quarters of A during Normalize type instruc-
tions is similar to that just described. The shift left decision is made if
A ^ = A o as indicated by the G" (sigma) levels.
1.9 1.0
Note that if there is to be a shift right it will occur at AK^, . At the com-
pletion of the shift right, A. ^ 7^ A. q (see Fig. 1^1-^3 for the NOE logic that
-, 1.9 i-o
complements A. at AK~ ), therefore the cr (sigma) levels will be absent and
i.9 0'.2 -j^
' no shift left will occur at AK 1 •
March I961 lij-29
The shift logic for the SHA type instructions is similar to that for the NOR type
instructions. The shift right decision is made if the operand sign bit is
negative (Y = D ), and left if the sign bit is positive (Y. = D. ). Note
i i.9 1 1-9
that FD is used both for inhibiting the counting in D and for inhibiting the
shifting in the SH instruction.
A shift left in the active quarters of A occurs in the DlVide instruction. A
shift occurs during each iteration as ASK counts up to zero. During the count up
to zero, ASK is in the OWE state. One more shift occurs after ASK reaches the
zero state. This shift is taken care of by the ASK term.
lij-5.3 B REGISTER SHIFT RD LOGIC. (See Fig. li<-35)- The B register shift logic for the
NAB and SHB instructions is identical to the A register shift logic for the NOR
and SHA instructions, respectively. During the MUL instruction, a shift right
occurs in all the active quarters of B at AK^ „ • Similarly, during the DIV
instmction, a shift left occurs in all the active quarters of B at AK^ .
ik-'^.k MULTIPLY STEP RD LOGIC. (See Fig. lh-36) . The Multiply Step pulses are fired
off repeatedly during the MUL instruction. The two pulses involved are:
I MULT STEP ^ ^ ^ ^ rjij^^g pulse is fired off in all the active quarters.
i i
Note that this pulse effects only bits i.l through i.8.
I MULT STEP SIGN
A , C . This pulse is fired off only for those i.9
i.9 i.9
bits -which are not sign bits. The logic for the MULT STEP SIGN pulses
indicates that the pulse will be fired off for the i.9 bits, only if the
sign quarter of the subword is to the left of the quarter in which the i.9
bits are located.
li]-5.5 COMPLEMENT C RD LOGIC. (See Fig. lk-3T) . This logic is not currently used. The
complement nets have, however, been partially incorporated in the computer.
I CRY
X-r-^.w ^^u.x^ xvx. ^^^s.^. V— --&• -—J-/- -----B - ---■ -""--^--"^"", " ►pulse
Will be fired off in all the active quarters of A. Note that DIV uses a twos -
complement arithmetic. The logic of this arithmetic leaves the carry loop open
(see Fig. lU-28(b)).
The DIV instructions involve an "end around carry". The logic involved closes
the carry loop (see Fig. lJ+-28(a)). If the subword in A contains all ONES, the
loop tends to exhibit instability in the presence of noise. That is, it can
generate a carry level by itself. For this reason, the I ►pulse is not
fired off in a quarter if the subword containing it holds all ONES. For example,
the L^SI-^A pulse is not fired off unless: (l) either A does not contain all
CITIES; or (2) A. does not contain all ONES and there is an f^ (36) or f^ (l8,l8)
ill -30 March I961
fracture; or (3) A does not contain all OEES and there is an f (36) fracture;
or (^) if A, does not contain all OWES and there is an f (36) fracture.
lij-5.7 PARTIAL ADD KD LOGIC. (See Fig. llj-39). The execution of the MUL instruction
involves the iteration of a "partial add - multiply step" loop. The loop looks
somewhat as follovs:
Exit
The PAD pulse ^ encountered before the loop is entered^ occurs at AK„ _:, while the
1
PAD pulses in the loop occur at AK„ _ •
PAD 1 1 on Fig. 1^1-39 pertains to the MUL instruction. The logic ANDed with
PAD II says that the i-th PAD pulse is fired off if the rightmost hit in the
suhword in B is in the OWE state and the i-th quarter is active. For example, a
partial add pulse is fired off in quarter i+ if an f (27,9) fracture is involved
and the B hit is in the OWE state at (AK^ o "^ ^ 2^'
The execution of the DIV instruction involves the iteration of a "partial add -
carry" . The ' loop in this case looks somewhat as follows :
Entrance
PAD
Exit
while
The PAD pulse, encountered before the loop is entered, occurs at AK_ _;
1
the PAD pulses in the loop occur at AK •
B.9
PAD j 2 pertains to the DIV PAD pulse that is fired off before the loop is
entered. Wote that this pulse is fired off in all active quarters.
March I961
li^-31
PAD pertains to the DTV PAD pulses that are fired off in the loop. The
early pulses in the loop are conditional on the state of the ASK counter and the
— ^ 1.
fact that the quarter is active. Notice that RN. —-^ a . The last PAD pulse
fired off is conditional not on ASK^ but on the sign of the subword. This is
■why the PAD 0's must be ANDed vith the subscripted Roman numerals and not just
the activity levels. As ASK counts ;, PAD looks at ASK^, ASK and A . Thus,
ASK COIMTER
1111110 ASkJ Z) PAD 0. where i = 1,2, 3. ^^
1111111 ditto
ASK^ 'ZD PAD where i = l,k,3^^
1 i
1 ASK.^ j^ ONE, ASK ^ ZERO, . " . PAD 0. !!> A°
( 1 11.9
PAD I 2 also takes care of the single partial add pulse that is fired off in
the DSA, ADD and SUB instructions at AK„ .
1I+-5.8 A,B,C AND D CLEAR RD LOGIC. (See Fig. lU-il-O) . First consider the I — ♦.A,B,C
and D levels which cause the ' ►A,B,C and D pulses to be fired off. These
levels are triggered by QK time levels . If an operand is to be stored in the
Arithmetic Element registers of the V Memory, the selected register will first
220!
be cleared at QK . The A register is also cleared in the ITA and INS
220:
instruction at QK .If the Arithmetic Element registers are to be loaded,
they will first be cleared at QK .
The active quarters of A will be cleared in a MUL instruction at AK • This
occurs immediately after the contents of A have been treuisf erred into B, i.e.,
at AK^_^.
The active quarters of C will be cleared in an ADD or SUB instruction at AK^,
just before the PAD pulse is fired at AK„ ^. These quarters of C will also be
^"^ 1 1 lO
cleared in the MUL and DIV instructions at both AK., , and AK o- The " — ►C.
"I lO u-.o 1
at AK"^ sets up C for the first PAD pulse. The I ► C. at AK o leaves C
CZ.l X ^. o
cleared in both the MUL and DIV instruction at the end of the instruction. In
the case of the DIV instruction, it also clears C at the same time the carry
occurs .
1^-32 March I961
lll-5.9 Z PULSE GATE LOGIC AM) KD LOGIC. (See Fig. l^J-Ul) . See Fig. ik-k for the function
of Z in the various instructions. Z is cleared in the sign quarter at the begin-
ning of the ADD, SUB and MUL instruction. This occurs at AKq,^^. Note that in
the case of DIV an 1^.9 ^^%. \ pulse is fired at AK^_^- If the sign hit is
positive ( A. °), Z is cleared to ZERO; if the sign bit is negative {\q)^ Z
is set to ONE.
In the case of SCA, SAB, WOA and NAB, the instruction leaves Z cleared. The
clearing occurs at AlC*" . MULtiplication always leaves Z cleared. In the MUL
case, Z is cleared at AK^, •
In the case of MULtiplication, Z is cleared at AK^^^ and then the sign of A is
placed in Z at AK""" • In the case of DIV, an overflow can occur. This is taken
care of by reading the sign of A into Z near the end of the instruction, i.e.,
^^ "^a.ll*
The rest of the Z logic is used in the ADD and SUB overflow logic (see Fig. ih-^) .
Z is first cleared at AK^ ^. The signs of D and A are compared at AK^^^- If
they are the same, Z is set to ONE. The A register contains the addend or sub-
trahend at AK"^ . At the same time the signs are examined, the PAD pulse is
fired off. After the carry is completed, the A register contains the s\m or
difference. At AK"^ the sign of D and A are again examined. If they are the
same, Z is cleared by the Reset Z logic. If they are different, the ONE left
in Z indicates an overflow condition.
11^-5.10 A REGISTER COMPLEMENT RD LOGIC. (See Fig. ll+-i^2). The subword will be com-
plemented at the end of the MUL and DIV instructions if Z ^ Y in the sign
quarter, i.e., at AK^^^ and AK^^^^. respectively.
In the DIV instruction, A is complemented at the beginning of the instruction at
AK , if the sign of the subword is positive.
A is also complemented during the INS and ITA instructions as part of the
execution logic .
Note that • ► A. complements A. through A .
In addition to complementing the quarters of A, it is possible to complement the
A bits -individually. In SCale instructions, if an overflow from a previous
i.9
instruction exists in the sign quarter, the sign bit in A is complemented. If
the scale instruction calls for a shift left (Y°), the sign bit is complemented
at AK"^ . If the SCale instruction calls for a shift right (Y^), the sign bit
is complemented at AK^, _ •
March I961 1^-33
Finally, in a NOR instruction, the sign bit of A is complemented if an overflow
from a previous instruction exists in the sign quarter. This occurs at AK •
1^1-5.11 B REGISTER COMPLEMENT RD LOGIC. (See Fig. l^J-ij-S). If a negative subword is
placed in the B register in a MUL instruction, the subword will be complemented
in the B register. This occurs just after the multiplier in the A register has
been transferred into the B register, i.e., at AK • Thus, MUL is always
executed with a positive multiplier in the B register.
During a MUL instruction, the B register is also complemented at the end of the
AK cycle, i.e,
control logic
AK cycle, i.e., at AK _, if Z is not equal to Y. This is part of the sign
In a DIV instruction, the minor half of the dividend, located in the B register,
is complemented at the beginning of the instruction, i.e., at AK , if the sign
of the major half of the dividend located in the A register is positive. This is
i C
the significance of the I ^B. • EN. logic. The B register is also complemented
at the end of the instruction when it contains the remainder, if the Z flip-flop
in the sign quarter of A is in the ZERO state at AK .
^. 11
loa 2ia
The B register is also complemented in the INS instruction at QK and QK
as part of the execution logic of that instruction.
lij-5.12 D REGISTER COMPLEMENT RD LOGIC. (See Fig. lU-i^■l^■). Consider first the complement
D logic used in the NOR instructions. Since D counts up to zero, the mem^ory
operand in D is always complemented at the beginning of the NOR instruction,
i.e., at AK_, _• The D register is then complemented at the end of the normalizing
Q-.3
to restore the operand to its original value. The end of the normalizing occurs
when A n 5^ A ^ in the sign quarter, i.e., n-' ., hence the (RN + (7— ) factors.
i.b 1.9 1
If the data to be normalized should contain all ZEROS or all ONES, ASKg • ASK,
would indicate the end of the normalizing, i.e., ASK overrides the D counter and
the cr' condition is ignored.
The logic for complementing the D register in other instructions is basically
covered by the terms. First consider the SH type instructions, i.e., the SCale
and CYcle instructions. The sign quarter of D is complemented if the sign of
that quarter is positive, i.e., the sign quarter (which is the quarter in which
the counting occurs) is always made negative. The logic shown on Fig. lU-UU
may look peculiar for these instructions until the following facts are realized:
Q and Q are used only in the logic for quarters 1 and 3j respectively: whereas
and Q, are each used in the logic for more than one quarter. Therefore, the
SH terms for quarters 1 and 3 can be included in Q and Q , respectively; whereas
separate terms are needed for quarters 2 and \.
1^-3^ March I961
Now consider the iDalance of the logic. Remember that AKIR covers both the
ADD and SUB instructions . In a SUB instruction the active quarters of D are
complemented at AK • At AKT , the active quarters of the subword in D are
complemented in the ADD and SUB instruction, if the sign of the subword at this
time does not equal Y, i.e., Y. y^D. . Note that in SUB D is complemented twic
whereas in ADD D is complemented just once .
In the DIV instruction, the data in the D register is always made opposite in
sign to the data in the A register before the partial addition occurs, i.e., D
is complemented if D. ^ = A. ^ at AK^ ^. Remember that the PAD pulse is fired
-, ^'9 J. 1-9 '^•^ 1
off both at AKZ ^ and AKT ^. Therefore, D is complemented at AK for the same
p. 3 p-9 ]_ "-y
reason. Finally, D is complemented at AK^, as part of the sign control logic
if Y 7^ D. . This makes the sign of D equal to its original value.
In the MUL instruction the D register is complemented at AK if the subword in
1 1
D is negative, i.e., if Y . The D register is complem-ented again at AK if
1 ^-y
Y in order to restore D to its original value .
llj._5.i3 E ►A, B, C AID D RD CONTROL. (See Fig. \h-h'y) . The only way that data can
be placed in the A, B, C and D registers in the Arithmetic Element is via the
Exchange Element, more specifically via the E register. This occurs in the
following situations:
1) During LD type instructions, when the A, B, C or D registers are
specified, the transfer occurs at QK
2) In the execution logic of the ITA and UNA instructions, the data found
230;
in E at OK is transferred into the A register.
3) If a STORE instruction involving the V^^ Memory specifies one of the
Arithmetic Element registers, data is transferred from E into the
rs 23a
register at QK
As we saw earlier in the chapter the data that is transferred from E^ into
D is also transferred by the same register driver pulse into Y. .
i.9 1
Yh-'^.Xh A — 3— ► B AND B -^ — ► A RD CONTROL. (See Fig. 1^4-^6). Note that these
transfers are of the jam type. They occur in the MUL and DIV instruction imder
the following circumstance:
1) One of the first things that happens in a MUL instruction is that the
data in the active quarters of A (left from a previous Instruction) is
transferred into the corresponding quarters of B. This occurs at -^q-^-l'
March I961 1^-35
2) The execution logic of the DIV instruction generates the quotient in the
B register and the remainder in the A register. At AK^, the active
quarters of A and B are interchanged so that A contains the quotient and
B contains the remainder.
lk-36 lykrch 1961
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"CHAPTER 15
IN -OUT EIJMENT
TABLE OF CONTENTS
15-1 INTRODUCTION
15-2 IN-OUT ELEMENT BLOCK DIAGRAM
15-3 PHYSICAL LAYOUT OF THE IN-OUT ELEMENT
15-3.1 GENERAL DESCRIPTION
15-3.2 IN-OUT BUS
15-3.3 CABLE INTERCONNECTIONS BETWEEN CENTRAL COMPUTER AND IN-OUT SECTION
15-3.3.1 SEQUENCE SELECTION CONTROL CABLES
15-3.1+ CABLE INTERCONNECTIONS BETWEEN IN-OUT SECTION AND IN-OUT UNIT
15 -U TYPICAL IN-OUT UNIT
15-U.l GENERAL DESCRIPTION
15-i;.2 CONTROL FLIP-FLOPS
15-4.3 SYNCHRONIZER
15-5 TYPICAL SEQUENCE SWITCH
15-5.1 GENERAL DESCRIPTION
15-5.2 LOGICAL STRUCTURE
15-5.3 SEQUENCE SWITCH LOGIC
15-6 IN-OUT ELEMENT OPERATION CODES (TSD AND lOS)
15-6.1 GENERAL DESCRIPTION
15-6.2 TSD AND lOS TIME CONTROL SIGNALS
15-6.3 lOCM CONTROL LEVELS
15-6. i]- lOS
15-6. 1^.1 lOS TYPES
15-6.4.2 lOS 3X XXX FLOW DIAGRAM
15-6.5 TSD
15-6.5.1 TSD TRANSFER MODES
15-6.5.2 TSD FLOW DIAGRAM FOR OUTPUT DEVICE
15-6.5.3 TSD FLOW DIAGRAM FOR INPUT DEVICE
15-7 ALARMS
15-8 DESCRIPTION OF IN-OUT UNITS
* (00^
STARTOVER
* ikl'
10 ALARM
(1+2'
TRAP
(1+6
MAGNETIC TAPE
(1+7'
MISCELLANEOUS INPUTS
(50
DATRAC
(51
) XEROX
* (52
) PETR
(54
INTERVAL TIMER
(55
) LITE PEN
March I961
15-1
(60)
DISPLAY NO. 1
(61)
RANDOM NUMBER GENERATOR
* (63)
PUNCH
(65)
LINCOM WRITER INPUT
(66)
LINCOLN WRITER OUTPUT
(7-2)
X-Y PLOTTJilK
* Discussions currently included in chapter.
LIST OF FIGURES
15-1 BLOCK DIAGRAM OF IN-OUT ELEMENT SHOWING INTERCONNECTIONS WITH CENTRAL COMPUTEIR
15-2 INTERCONNECTIONS BETWEEN SEQUENCE SWITCHES ON IN-OUT FRAME AND CENTRAL COMPUTER
15-3 INTERCONNECTIONS BETWEEN SEQUENCE SWITCHES ON IN-OUT FRAME AND INDIVIDUAL IN-OUT UNITS
15-U INTERCONNECTIONS BETWEEN CENTRAL COMPUTER AND IN-OUT FRAME
15-5 TYPICAL SEQUENCE SWITCH
15-6 LOGICAL OPERATION OF INPUT MIXERS AND OUTPUT DISTRIBUTORS USED IN SEQUENCE SWITCH
15-7 SIMPLIFIED FLOW DIAGRAM FOR TSD AND lOS INSTRUCTIONS
15-8 IN-OUT TIME CONTROL LEVEI£ GENERATED IN CENTRAL COMPUTER
fxx )
15-9 lOCM^ ^ LEVELS AS A FUNCTION OF SELECTED SEQUENCE
15-10 lOS TYPES
15-11 lOS REPORT TABLE
15-12 SIGNIFICANCE OF nJ^ % _ DURING lOS 3X XXX AND lOS 6X XXX
1.1-2.3 1
15-13 FLOW DIAGRAM FOR lOS 3X XXX WHEN REPORT BIT IS SET (CF )
15-1^4- lOCM MODE LEVELS ASSOCIATED WITH EACH IN-OUT UNIT
15-15 TSD DATA TRANSFER TABLE
15-16 PETR READING INTO MEMORY BLOCK OF 36 BITS IN ASSEMBLY MODE
15-17 TSD FOR OUTPUT DEVICE
15-18 TSD FOR INPUT DEVICE
15-STARTOVER-l STARTOVER SEQUENCE
15-10 ALARM- 1 BLOCK DIAGRAM OF 10 ALARM SYSTEM
15-10 ALARM-2 ALARM DATA REPORTED BY TSD
15-PETR-l PETR TAPE TRANSPORT SYSTEM
15-PETR-2 PETR BLOCK DIAGRAM
I5-PETR-3 PETR MOTION CONTROL LOGIC
15-PUNCH-2 PUNCH BLOCK DIAGRAM
15-PUNCH-2 HIGH SPEED PUNCH SYNCHRONIZATION
15-2
March 19 61
CHAPTEE 15
IN-OUT ELEMENT
15-1 INTRODUCTION
The In-Out Element provides a communication link between the external world and the
computer. Before events occurring in the external world can communicate with the
computer they must be synchronized, i.e., brought in step with the periodicity of the
computer. This synchronizing occurs in the In-Out Element.
All of the in-out data transmission devices, as well as certain asynchronous events such
as in-out alarms and those events initiated by certain manual controls, communicate with
the computer via the In-Out Element. However, some asynchronous events, such as most of
those initiated at the control console, communicate directly with the Control Element.
The In-Out Element must provide the necessary logic for accommodating the special oper-
ating characteristics of many different devices . It is this accommodation requirement
that makes the In-Out Element such a complex communication link.
As described in Chapter 3> the solid state circuitry used in the In-Out Element is
slower than the circuitry in the central computer. The logic reflects this, and also
the fact that level transitions and O.k microsecond levels are used to generate pulses.
The chapter begins with a block diagram discussion of the In-Out Element. This discussion
establishes the basic components and communication paths.
Because the in-out frame has a rather complex physical structure, the layout of the
In-Out Element is discussed in some detail.
A discussion of a typical In-Out unit and sequence switch then follows, since these
components are found in all sequences and have common characteristics regardless
in which sequence they are found.
The two In-Out OP codes, lOS and TSD, are then discussed. The logic and communication
paths these OP codes use are discussed in detail.
The chapter concludes with a logical description of the individual In-Out \mits .
15-2 IN-OUT ELEMENT BLOCK DIAGRAM
Fig. 15-1 shows a block diagram of the In-Out Element. The diagram indicates the
communication paths between the In-Out Element and the central computer.
March 1961 15-3
The In-Out Element includes:
1) Input-Output Devices
2) In-Out Bus
3) Sequence Switches
Since only one In-Out device can commimicate with the central computer at a time, it is
possible to have all the devices use a shared In-Out Bus. An elaborate switching arrange-
ment is required to properly connect the selected In-Out device to the hus . This
switching is taken care of by the individual sequence switches associated with each
In-Out device .
Once an In-Out device is properly connected to the In-Out Bus, it can communicate with
the central computer. While it is difficult to make a sharp distinction, generally the
communication will involve transmitting either data information or control information.
Each bus between the central computer and the In-Out Element is used to transmit a
specific type of information. For example:
lOBM Bus - This bus is used to transmit data information from the
In-Out Buffers to the E register. It is also used to
"report" the control state of the In-Out devices to the
E register.
E Bus
This bus is used to transmit data information from the
E register to the In-Out Buffers .
N Bus
This bus is used to transmit mode control information
from the N register to the In-Out devices .
lOCM Bus - This bus is used to transmit control information from
the In-Out devices to the Control Element in the central
computer.
Hi Speed Bus - This bus is used to transmit control information from
the Control Element to the In-Out Devices .
Note that tl^ese buses are "shared" by all the sequences. In addition to these shared
buses, there are individual cables that ran between each sequence switch and the Sequence
Selector in the central computer. These cables transmit the "Raise Flag" signals to the
Sequence Selector from the In-Out devices. They also transmit KD and ND sequence
selection levels to the sequence switches during TSD's and lOS's, respectively. (The
Mio)
function of KD
will be discussed later.)
15-1^
March I961
15-3 PHYSICAL LAYOUT OF THE IN-OUT ELEMENT
15-3.1 GENERAL DESCRIPTION. An elaborate cabling and busing arrangement is required to
interconnect all the parts of the In-Out Element to the central computer. This
results in the In-Out system being physically complex as "well as logically
complicated .
The heart of the cabling and busing arrangement is the In-Out Frame. This frame
or section is located at the far left end of the central computer structure
(facing the front). The frame contains an open vire bus structure and all the
sequence switches associated with the various In-Out devices. Flexible cables
connect the In-Out section to the central computer and to the individual In-Out
devices. Note that the individual In-Out devices themselves can consist of
several chassis and control panels and require extensive interconnection. An
example of this is the XEROX printer. Fig. 15-2, 15-3 and 15-U show the cable
interconnections for all the sequences .
15-3.2 IN-OUT BUS. There are two open-wire buses running horizontally down the In-Out
section (see Fig. 15-2). The top bus has 100 wires and the bottom bus has 72
wires. Each bus has 37 positions where lO^i-pin receptacles and 75-pin receptacles,
respectively, provide access to the buses for external connection. Since all 37
receptacle locations are logically identical, convenience alone determines which
sequence is assigned to which location. Signals from the central computer are
routed into the In-Out Bus at the left end of the In-Out section (looking at the
section from the rear). Signals to the central computer are routed from the
In-Out Bus at the right end of the In-Out section.
A 10-conductor video cable is jumpered between the T bars on the In-Out section
occupied with sequence switches (see the jumper between Sequence 66 and 72
identified on Fig. 15-2). This video cable is the In-Out High-Speed Control Bus.
It also runs horizontally down the In-Out section.
In addition to the cable terminating devices found at either end of the In-Out
1 , -r^^.^IA + MISIND
section, there are two logic nets involving lOBlV^ and lOCM . ihese
nets will be discussed latei: in the chapter.
15-3.3 CABLE INTERCONNECTIONS BETWEEN CENTRAL COMPUTER AND IN-OUT SECTION. These inter-
connections are shown in Figs. 15-2 and 15-^- The E cables from Section BC in
the central computer terminate in cascodes and cable drivers on the In-Out
section. The E cables consist of four 10-conductor video cables, which are used
for transmitting eJ _ 1 1 ^36 wires). These cables connect into the 100 wire
bus .
March 1961 15-5
The N cables from Section BC terminate in cascodes and cable drivers. These in
turn connect into the same 100-vire bus that the E cables connected into. The
W cables consist of two 10-conductor video cable for transmitting Np ^
(18 wires). Although all 18 bits appear on the bus, only bits 2.3 - 1-1 are
currently used. Note that both ZEEOS and OKES appear on the W bus since the
N cables are tied both directly and through inverting amplifiers to the N bus .
The lOCM cable to the Control Element in Section C of the central computer is
driven by cascodes and cable drivers . These amplifiers are plugged into the
100-wire bus at the right-hand end. The E, W and lOCM cables all interconnect
with the 100-wire bus .
The 75-wire bus transmits only lOBM, ' (72 wires). Information is carried
back from the lOBM bus to the E register via section BC in the central computer.
This is done using eight lO-conductor lOBM video cables.
15-3.3.1 SEQUENCE SELECTION CONTROL CABLES. Each sequence switch on the In-Out
section is connected by an individual cable to the Sequence Selector
in Section D of the central computer. These cables transmit the KD , ,
KD""" and [RAISE FLAG, signals. In addition to these, a KD ^ ■^ wire
is found in each cable.
15-3. U CABLE INTERCONNECTIONS BETWEEN IN-OUT SECTION AND IN-OUT UNITS. These inter-
connections are shown on Fig. 15-^. As the figure indicates, considerable
variation occurs in the niimber of cables required for each sequence. Basically,
the cables are used to connect the In-Out units to the associated sequence
switches on the In-Out section.
The sequence switches themselves provide the link between the cables shown on
Fig. 15-3 and the In-Out Bus itself.
15 -U TYPICAL IN-OUT UNIT
15-U.l GENERAL DESCRIPTION. A typical In-Out Unit consists of the following types of
devices :
1) Data Conversion Devices. For example, a photoelectric tape reader, a
paper punch, etc .
2) Control Boxes. These boxes usually contain the In-Out buffer, the
synchronizer, the control flip-flops and other special purpose circuitry.
3) Non-logical Controls. These are found in various chassis and control
panels and include such items as power supplies, motor switches, etc.
15-6 March 1961
15-^.2 CONTROL FLIP-FLOPS. These flip-flops determine the logical operation of the
In-Out unit. The standard In-Out control flip-flops are:
C (Connect Flip-Flop). The In-Out unit is logically connected to the
computer by setting the C flip-flop to OWE. This is done hy an lOS
"connect" instruction. C gates the EAISE FLAG signals and, usually,
certain other signals such as those caused by the Equipment Inability
Alarm (EIA) flip-flop and the MISINDication flip-flop being set.
Almost all In-Out units have a connect flip-flop.
ST (STatus Flip-Flop) . When this flip-flop is set to ONE, it is
permissible for the computer to perform a TSD in the' unit's program
sequence. The STatus flip-flop is set to ONE by the In-Out unit
generating a "completion pulse", indicating that the unit is ready
for another TSD. Almost all In-Out units have a STatus flip-flop.
EIA (Equipment Inability Alarm Flip-Flop) . This flip-flop is set to
ONE as a result of some difficulty such as overheating, low paper
supply, etc., in the associated In-Out unit. Not all units have an
EIA flip-flop.
MISIND (MISINDication Flip-Flop) . This flip-flop is only found in
free-running units such as the Magnetic Tape unit. When MISIND is
set to ONE, it indicates that the unit is getting ahead of the
computer, i.e., a line of data has been missed by the computer.
M (Maintenance Circuit). This is not a flip-flop, but rather a circuit
which may include a manually operated maintenance switch. A "fail- safe"
design has been incorporated in the circuit, so that an M (Maintenance)
level is generated when any one of several conditions occur. Thus an
M level is generated when the switch is open, the unit is not powered
or the unit is physically disconnected. The transition of this level
does not have to be synchronized.
I5-U.3 SYNCHEONIZER . Normally when an In-Out unit has completed its cycle, it will
generate a completion pulse.' This pulse indicates that the unit is ready for the
central computer to execute another TSD. These completion pulses occur
asynchronously, since in many cases they occur as a function of the mechanical
cycle of the data conversion device itself. The central computer synchronizes
these asynchronous events by means of lOI clock pulses and a synchronizer. As
we shall see later in the chapter, the output of the synchronizer becomes the
synchronous RAISE FLAG signal that is transmitted to the central computer. The
function of the synchronizer is to insure that the In-Out buffer state will not
change until the central computer has completed its communication with the buffer.
March 1961 15_Y
15-5 TYPICAL SEQUENCE SWITCH
15-5.1 GENERAL DESCEIPTION. Since a large amount of information is transmitted between
the In-Out Element ajid the central computer, it is important to understand hov
this information is routed to its correct destination. Most of this routing
occurs in the sequence switches . The sequence switches provide a method of
multiplexing a number of In-Out units onto a "shared" bus .
One side of the sequence switch is tied to the central computer. The other side
of the sequence switch is tied to the associated In-Out unit. All the information
on the "shared" buses will appear at the input to every sequence switch. It is .
then only necessary to provide a logical means for selecting the specific sequence
switch that will pass the information through to the In-Out unit. In certain
cases information will be transmitted right through the sequence switch without
any gating occurring, e.g., this occurs in the case of lOI clock pulses,
I PRESET ^ IOC levels, etc.
15-5.2 LOGICAL STRUCTUEE. The sequence switches vary in complexity, depending on the
nature of the specific sequence. However, there is much that is common to all
the sequence switches. Fig. 15-5 is a block diagram of a typical sequence switch.
It shows in composite form most of the communication that is possible between the
central computer and the In-Out Element, and indicates the kinds of sequence
switch gating which can occur.
The two standard "mixing" packages that are used in the sequence switches are
the input mixers (IM) and the output distributors (OD). (The output mixers (OM)
are logically similar to the output distributors.) The logical operation of
these packages is shown in Fig. 15-6. These are level logic devices, although
a 0.^ microsecond "pulse" is often used as one of the input signals.
15-5.3 SEQUENCE SWITCH LOGIC. No action can take place in the sequence switch during
a TSD or lOS unless the sequence is selected by the KD or KD levels,
respectively. The control levels gated by KD and ND are shown in Fig. 15-5 •
They include the control inputs transmitted to the sequence switch over the
In-Out High Speed Control Bus and the lOCM levels transmitted from the In-Out
units to the central computer. Note that in the case of the input signals, the
levels retain their identity after passing through the selection logic nets,
except that the KD's and ND's are dropped. For example:
15-8 March I961
Sequence Switch
Input
t MODE + SELECT
WD
Corresponding
Sequence Switch
Output
I MODE + SEI.ECT
♦■ IOC
KD
lOB
lOB
The lOCM levels are expressed in terms of the control logic producing them. For
example :
Sequence Switch
Input
ST
Corresponding
Sequence Switch
Output
loc:
^
As mentioned before^ certain control signals pass through the sequence switch
without "being gated by KD or ED . These are the lOI clock pulses^ and the Stop
Unit and Preset levels to the In-Out unit; and the RA.ISE FLAG pulses, and the
_MAIT MISIED EIA
lOCM , lOCM and lOCM levels to the alarm sequence. The reset signal
is gated by M so that, when the In-Out unit is in the maintenance state, the
PRESET button on the console will not disturb the unit.
The specific logic used to connect the In-Out buffer to the E bus, the lOBM bus
to the In-Out buffer and the In-Out control, and the N bus to the In-Out control
1 be discussed later
he chapter
lowever, the general features
logic will be pointed out at this time.
Data can be transferred to and from the In-Out buffer in three possible modes:
the NORMAL mode, the ASSEMBLY AND FORWARD mode and the ASSEMBLY AND REVERSE mode.
Once the mode transfer is determined, the sequence switch is set up accordingly.
Data is always transmitted to the In-Out unit by first clearing the unit's buffer
and then transferring OKES. For this reason, the output distributors have only
'one output wire. Data is usually transferred from the E bus to the In-Out unit
in the form of a 0.^ microsecond ground level. The strobing is performed by a
O.U microsecond negative (-3 volts) level.
Information is "jammed" into the E register from the lOBM bus. For this reason,
input mixers are designed with two outputs . When the gating level is at ground,
both outputs are at ground regardless of the input. When the gating level is
negative and the input is at ground, one of the outputs will be at ground and one
'will be negative. If the input goes negative, the output wires will both reverse
their signal levels. Hence data is visualized as represented by the negative
output wires .
March I961
15-9
15-6 IN-OUT ELEMENT OPERATION CODES (TSD AND lOS)
15-6.1 GENERAL DESCRIPTION. Fig. 15-7 shows a simplified flow diagram of the TSD and
lOS instructions .
During the execution of a program there is constant communication back and forth
"between the In-Out Element and the central computer. That this can occur in a
variety of ways will become apparent in the discussion that follows.
Suppose that an lOS is executed which logically connects the i-th sequence. This
can occur as follows . The lOS will cause the ND level to be generated in the
Sequence Selector. The ND level will then allow the N register to coramixnicate
with the i-th control flip-flop via the i-th sequence switch. In this way the
information in the N register during an lOS can be used to set the state of the
i-th control flip-flops and in particular logically connect (C ) the i-th
sequence .
At certain specific times the Control Element will transmit lOI clock pulses to
all the synchronizers in the different In-Out units . These lOI clock pulses
"synchronize" the asynchronous events in the In-Out device that are used to
indicate the devices have completed their cycle and are ready to communicate with
the central computer. If a sequence is logically connected (C ), the output of
its synchronizer will be transmitted to the Sequence Selector in the form of a
I RAISE FLAG pulse. At the same time, if an input device is involved, the
output of the synchronizer will be used to gate data from the input device into
the In-Out buffer in preparation for a TSD.
The Sequence Selector may receive "Raise Flag" signals from several sequences,
since more than one sequence can be logically connected at a time. The Sequence
Selector logic then determines which sequence has the highest priority. When
all the necessary conditions are satisfied a change of sequence will occur to the
selected sequence. At that time the KD level will be generated. VThen a TSD now
occurs in the program of the current sequence, KD will allow TSD timing control
information to connect the E register to the i-th In-Out buffer at the right
logical time, if an output In-Out device is involved. If an input device is
involved, the i-th In-Out buffer will be connected to the lOBM bus by the KD
level and the TSD time control. The precise time at which the buffer content is
read into the E register will then be determined by the lOBM — ^ — ► E pulse
that is generated by an E register driver.
Note that the mode in which data is transmitted during the TSD is determined by
an earlier lOS. The states of the i-th control flip-flops are transmitted back
to the central computer in the form of lOCM levels . These lOCM levels set up
the necessary logic for transmitting data in the mode called for by the lOS .
15-10 March I961
15-6.2- TSD AND lOS TIME CONTROL SIGNALS. The logic generating the TSD and lOS time
control signals shown on Fig. 15-7 is tabulated on Fig. 15-8. The logic generating
the lOI clock pulses and the IPKESET ^ IOC and STOP UNIT levels is also shown on
Fig. 15-8.
The time signals originate in the Control Element of the central computer and
are transmitted over the 10 High Speed Control "bus to the sequence switches .
The lOI clock pulse and Stop Unit signals pass through all the sequence switches
without any gating occurring there . The IPEESET ^ IOC level is gated through
the sequence switches hy an M (Maintenance) level that indicates the sequence is
not disabled. The rest of the time control signals enter only those sequence
switches selected by ND during an lOS or KD during a TSD.
Note that normally two lOI clock pulses occur during each PK cycle . These clock
pulses are inhibited;, or prevented from occurring, if the QK cycle of a previous
Oia 12a
TSD overlaps the current TSD-PK cycle at PK or at PK . An lOI clock pulse
lia
will also occur at CSK during a delay synchronization cycle if the DSK cycle
is to be followed by another DSK cycle, i.e., if the ( lO ^ CSK^) at CSK
logic is satisfied. These lOI clock pulses are used to synchronize the asynchro-
nous completion pulses in the In-Out devices and, in so doing, to generate the
"Raise Flag" signals at the proper time.
During an output TSD, the In-Out buffer is cleared during the operand cycle by
the * ♦ lOB level at QK . The data in the E register is then- transferred
into the In-Out buffer by a ' ^ ♦ lOU level at QK^ , During an input TSD,
KJJ
the In-Out buffer is connected to the lOBM bus by the lOB — ♦ E level. The
data is then pulsed into the E register by RD logic at the E register. It should
be noted that only the E bits corresponding to In-Out buffer bits are affected
by this strobe. The other E bits are left undisturbed. During an lOS, the
control levels generated depend on which of several possible lOS instructions is
being executed, i.e., on the value of N g , • If the lOS is to do anything
to an In-Out device, the bits must have the value Oil or 110. The lOS time con-
IMODE + SELECT ^ ^^^ ^ i SELECT ^ ^_„
trol level then generated will be :^ ♦ IOC . The ' — — ♦- IOC
,~jSEllCT~~I,\ ^ ^^ IMODE + SEI^CT ^ _^^ . ^ ,
level, or its inverse ( ' — ^^ ♦• IOC), gates the' ♦• IOC level at
the In-Out unit in such a way as to distinguish whether a "mode" or "select"
operation is involved. Note that this gating is significant only at those In-Out
units which have subunits (currently this only includes the magnetic tape
Oil
sequence). For all other In-Out units no distinction is made between ^26-28
^1° ...The l^
2.6 - 2.8 N
C to ZERO. Note, that, by definition.
and N^ o- ■ The '-^ ♦■ C level is used by the "disconnect" lOS to clear
2.6 - 2.8 ND
March I961 15-11
lOB — ♦• E = OKIE • EB
IOC — ♦> E = lOB
W KD
Hence,
IOC — ♦- E = OKIE "" + EB
These levels essentially determine whether the sequence switch is to be set up
to execute an lOS or a TSD . The logic is such that the IOC — ♦ E level
is always present, except during the QK cycle of a TSD when EB . In the TSD
case, the lOB — rrr ♦E level is generated. Thus the sequence switch is biased
KD
towards performing an lOS rather than a TSD .
I PRESET
The ' ♦■ IOC level is initiated by the PRESET pushbutton on the console.
This level sets all the In-Out control flip-flops to a prescribed state, which in
turn, in effect, places each In-Out unit in a predetermined state. The preset
state of the In-Out unit and its associated control flip-flops will vary from
sequence to sequence, but generally EIA, C, and MISIND will be cleared. The
STatus flip-flop will be set to ONE for an output unit, and cleared to ZERO for
an input unit . Normally, the In-Out unit itself will also be stopped .
15-6.3 lOCM CONTROL LEVELS. As shown in Fig. 15-7, the lOCM levels are used to inform
the central computer of the state of the In-Out unit. The central computer
reaches in to command the state of the In-Out unit by means of the N bus ; the
lOCM bus feeds back to the central computer the In-Out unit's actual state at
any moment.
The interpretation of the lOCM levels is, to an extent, a function of the sequence
selected. Note that if there is no sequence switch for the sequence selected by
the Sequence Selector, all the wires on the lOCM bus will float a t groun d. A
ground level indicates a not condition; for example, ground = lOCM = buffer
not busy. If a sequence switch is provided for the sequence selected, three
possibilities exist: (l) the level is tied to ground; (2) the level is tied to
-3 volts ; or ( 3 ) the level depends on the state of the In-Out control .
Fig. 15-9 tabulates the lOCM levels for all the sequences. The lOCM levels and
the logic that generates them are described below:
lOC:
M (Buffer Busy). In most sequences, this level is generated by C +
O / O 0\ o
ST (or, in some sequences, by M + C + ST ; . ST indicates that the In-Out
buffer is being used by the In-Out unit or that the In-Out tinit is in some
transient state and should not be disturbed.
15-12 March 1961
IOCm ( Mis indication ) . In free-running input devices ;, C • MISIND • M
will generate this level.
IOCm (Equipment InalDility Alarm). In sequences that have an EIA flip-flop,
M • C • EIA generates this level.
IOCM (note that NORMAL = Assemhly) . For sequences that operate in a
single mode, this level (or its negation) is prewired in the sequence switch.
NORMAL
In the sequences that can operate in more than one mode^, the IOCM
level is determined by the state of the mode control flip-flops.
When the In-Out unit is in the NORMAL mode, data is transferred in "blocks"
during a TSD, that is, adjacent bits in the In-Out buffer correspond to a
block of adjacent bits in the E register. In the Exchange Element, the
data is under normal permuted activity control (normal configuration control,
excluding sign extension).
If a TSD is performed in the ASSEMBLY mode, the In-Out buffer data is
splayed when it is transferred into the E register. That is, if there are
six bits in the buffer word, the bits will be spread out so that they
correspond to every sixth bit in the E register. Similarly, if there are
nine bits in the buffer word, the bits will be spread out to correspond to
every fourth bit in the E register. When a TSD is performed in the ASSEMBLY
mode, the Exchange Element is not under configuration control.
■pyprrm
IOCM (note that RIGHT = Left). This is a level used by the Exchange
iJORMAL
Element in conjunction with the IOCM level to determine whether data
in the E register will be shifted to the left or right into the M register
during an as sembly TSD . If the In-Out unit operates in the forward direction
(rev ), the lOCM^ "" level is generated; conversely, if the In-Out unit
1 RTCTTT
operates in the reverse direction (REV ), the IOCM level is generated.
IOCM (note that IN = Out). This level indicates whether the In-Out unit
is an input or output device. Note that for all sequences, except magnetic
IN
tape, this level is prewired in the sequence switch. The IOCM level is
used in the Exchange Element as one of the conditions for gating lOBM into
the E register during an input TSD instruction. The level is also involved
in the E to M transfer logic .
loc:
M (Maintenance). This level is generated whenever the In-Out unit's
maintenance switch is turned on, or the power is turned off. Note that the
level is not generated synchronously.
March I961 15-13
lOCm . This level is generated in the In-Out frame or section
by ORlng all the EIA and MISIND levels from the In-Out units. The fxmction
of this level vlll be discussed in the section describing the In-Out Alarm
Sequence .
Note that all of the above lOCM levels (or their converse) can be generated
by each and every sequence, and that all of these levels are transmitted to
the central computer at any given time only from the sequence selected by
KD . However, the central computer may or may not make use of the levels .
"RTPHT
For examp le, during a normal TSD, no use is made of the lOCM or
lOCM^^^™ levels.
15-6. J+ lOS. This instruction is used to control and/or report on the state of the In-Out
system, as well as to raise and lower flags in the Sequence Selector. It is one
of the variations of the OPE instruction. The instruction has the following
characteristics :
1) An lOS in any sequence can logically connect any other squence. For
example, an lOS in the PETR Sequence (52) can connect ( I 1 ^ C) the
Lite Pen Sequence (55)-
2) An lOS is always possible, i.e., the lOS is never prevented from
occurring, except when the selected In-Out unit is in the MAINTenance
state. An lOS 30,000 or 6o,000 will cause an lOSAL in this case.
3) An lOS instruction is always one of three types: i.e., it either (a)
affects the controls of an In-Out unit, (b) has no effect on any In-Out
unit, but raises or lowers a flag in the Sequence Selector, or (c) has
no control effect on either the In-Out Element or the central computer,
but is used for reporting.
i
1^-6. k.l lOS TYPES. lOS is an instruction in which some of the instruction
word bits are used in a special way. Fig. 15-10 shows how the content
of the N register is interpreted during an lOS .
, , , 00
The OP code bits 000100 (04) specify an OPE instruction. N □ p v
lOS AE ' '
indicates that an OPE instruction instead of an OPE instruction
is specified. Bits N, n 1, ^ are not used at all. The hold and defer
bits are interpreted in the usual way. The sequence selected by the
lOS is decoded from the J bits. CF (or Nj^ 0) is used as a "dismiss"
bit, i.e., if it is a ONE then the instruction reports a dismiss.
15_ll| March I961
CF (or W, , ) is a "report" Toit. If CF is a OHE, the state of certain
In-Out control flip-flops is reported to the E register. Fig. 15-11
tabulates the specific report made to the E register for each of the
sequences. For example^ suppose that an lOS ij-0^000^ specifying the
Datrac Sequence (50)j, is performed with CF . Then the content of FS
- 11
is placed in E. , ; the value of M • C • EIA in E , ; the content
of C in E^ ^ ; etc . Note that the transfer of the contents of the
2.6
control flip-flops to the E register is via the lOBM bus, and that,
when lOBM is gated into E, the E register hits take on the same state
as the corresponding lOBM hits . Here again the only E hits affected
are those that receive a report.
The Y hits are used to specify the lOS type. (Note that the decision
to dismiss or to report is independent of the lOS type.) Bits
Wp _ are used in only two of the eight basic lOS types determined
by bits W^^g _ 2.1^-
The basic lOS types are:
lOS 00 000, 10 000 and 70 000. If these lOS types have OF and
— D ^
CF , they become dummy instructions in which nothing happens, i.e.,
these lOS types can be used only for reporting.
lOS 20 000. This lOS type is used to logically disconnect the
selected In-Out unit from the computer.
lOS 3X XXX. This lOS type is used to logically connect the
selected In-Out unit to the computer and to specify the operating
mode of the In-Out unit. (Bits W specify the operating
mode.) Fig. 15-12 tabulates the mode specified by the N^
2.3 - 1.1
bits. For example, if the Punch Sequence (63) is selected and
W , then the ASSemblY flip-flop in the punch unit will be set
to ONE. If now a TSD is performed in the Punch Sequence, the data
will be transferred in the "assembly" mode.
lOS kO 000- This lOS type is used to lower the flag of the
specified sequence. It communicates directly with the Sequence
Selector and has no effect on the In-Out Element.
lOS 50 000. This lOS type is similar to lOS kO 000, except that
it raises the flag of the specified sequence.
March I961 15-15
lOS 6X XXX. This lOS type is used to select the sub-unit of a
multiple unit sequence. Currently only the Magnetic-tape Sequence
uses this instruction. Fig. 15-13 tabulates the magnetic -tape
suhunits selected by the N bits. Note that this lOS type does
not specify the operating mode of the selected subunit. This must
be done by an IDS 3X XXX. However, as noted earlier in the
chapter, lOS 6X XXX is equivalent to 3X XXX in those sequences
which do not specify subunits .
15-6. U. 2 lOS 3X XXX FLOW DIAGEAM. Fig. 15-13 shows an over-all flow diagram
for an lOS 3X XXX type instruction when the CF report bit is a ONE.
Note that certain of the N bits are used by the Control Element in the
logic that generates the lOS timing control.
The report data is gated onto the lOBM bus by the IOC ♦E level.
Note that this level occurs as soon as ND is decoded in the Sequence
Selector, i.e., the logic that generates IOC ♦ E does not include
a time level. The report data is then gated into the E register by
the lOBM — ^ — ► E pulse at the same time that the "mode commands" are
I MODE + SELECT ^^^
gated into the In-Out control flip-flops by the ' ♦• IOC
26
pulse, i.e., at PK
Note also the fact that the IOC ♦E level is generated is
sufficient to logically connect ( ' ♦■ C) the sequence, i.e., C is
1 1
set independent of the content of N. Since C • ST indicates that
the In-Out buffer is not busy the STatus flip-flop is always set to
ONE for an output unit and to ZERO for an input unit whenever the unit
is logically connected. Note that it is the transition to C
( <Cc > ) that sets or clears the STatus flip-flop.
If the maintenance switch is turned on (m), and either an lOS 30 XXX
or an lOS 6X XXX is attempted, an lOSAL alann will be generated at
2Ua
PK
15-6.5 TSD. This instruction transfers data between the specified In-Out buffer and
the selected Memory Element register. It is imlike the lOS instruction in the
following respects :
l) The computer must perform the TSD in the sequence associated with the
In-Out device into or out of which data is being transferred. This
sequence is determined by the content of the K register.
15-16 March I961
2) If the In-Out lonit selected for a TSD is not ready to receive or trans-
mit data, the TSD is not executed. In this case, a "dismiss and wait"
takes place . The central computer is Inf orm-ed of this condition "by
the "huffer busy" ( lOCM ) level.
3) The activity occurring in the In-Out Element during a TSD must be
synchronized with the central computer.
15-6.5.1 TSD TRANSFER MODES. One of the fundamental considerations in a TSD is
the mode in which data is transferred. A simimary of the modes for
each sequence is given in Fig. 15-lii-. Most of the sequences transfer
data in the NORMAL mode. The specific bits transferred in each sequence
and in each mode are given on Fig. 15-15-
A TSD in the PETE Sequence (52) can cause a data transfer in the
ASSEMBLY mode. This type of transfer is shown on Fig. I5-I6. It is
used to store a "block" of six 6-bit lines on the paper tape as one
36-bit word in memory by means of six successive TSD instructions.
Basically this is accomplished by transferring the In-Out buffer word
into the E register in a splayed form and then shifting the content of
the E register one bit to the left during the transfer from E into the
M register. In this manner, a series of six TSD's packs the six lines
into one memory word. The timing of the transfers and the logic of
the packing process are shown in Fig. 15-I6.
The Punch Sequence (63) is much like the PETE Sequence in that data can
be transferred in the ASSEMBLY mode. The logic involved is very
similar to that for the PETR Sequence, except that the direction of
data flow is reversed.
The Magnetic -Tape Sequence is unique in that it can transfer data in
any of the six possible modes:
1) Data can be transferred into the computer in the NORMAL mode.
2) Data can be transferred into the computer in the ASSEMBLY mode
with the tape traveling in the forward direction.
3) Data can be transferred into the computer in the ASSEMBLY mode
with the tape traveling in the reverse direction.
k) All three modes above are also possible when data is trans-
ferred out from the computer.
March 1961 15-17
15-6.5.2 TSD FLOW DIAGRAMS FOE OUTPUT DEVICE. Fig. 15-1? shovs a flow diagram
for a TSD when an output device is involved.
When the input device has completed the action requested by a TSD, an
lOI clock pulse will synchronize the "completion" pulse. A RAISE FLAG
will then be generated which will set the STatus flip-flop to ONE.
The RAISE FLAG pulse will also raise the sequence's flag in the
Sequence Selector.
When the Sequence Selector causes the central computer to change to the
In-Gut unit's sequence, KD will connect the In-Out unit to the In-Out
bus for a data transfer. As soon as the K Decoder decodes the content
of the K register, the lOCM mode levels and "buffer not busy" signal
will be transmitted to the central computer.
The lOCM level is generated, because the STatus flip-flop was set
before the KD"'' level was generated. The lOGM mode levels and the mode
control flip-flops will set up the Exchange Element and the sequence
switch, respectively, for the desired mode of data transfer.
IN
The fact that this is an output device (that is, that the lOCM level
is generated) means that a clear In-Out buffer pulse will be generated
at OK . The data in the E register is actually gated into the
v\r\ C^fYY
In-Out buffer by a ' ♦ lOU level occurring at QK .If required,
this ■ ♦ lOU level can also be used to Initiate the actual data
output conversion.
The ' ♦• lOU pulse will also clear the STatus flip-flop to ZERO and,
in so doing, will generate an lOCM (buffer busy) signal. This level
is used to inhibit the PK counter and cause a "dismiss and wait" . A
"completion" pulse from the output device will later indicate that the
TSD has been completed and that the luiit is ready for another TSD by
setting the STatus flip-flop to OME again.
15-6.5.3 TSD FLOW DIAGRAM FOR INPUT DEVICE. Fig. 15-l8 shows a flow diagram
for a TSD when an input device is involved. The process illustrated
is similar to that for an output device, except that the direction of
data flow is reversed. In this case, data is transferred into the
In-Out buffer from the input device when a completion pulse occurs.
This pulse is synchronized by the lOI clock pulses to generate a RAISE
FLAG signal. This RAISE F LAG signal sets the STatus flip-flop to ONE,
thus generating an lOCM^ (buffer not busy) level.
15-18 March I961
Note that the hiiffer is connected to the lOBM hus hy the lOB ^ E
level. There is no time level term in the logic that generates this
level. Consequently, the In-Out buffer is tied to, the hus for
virtually the entire QK cycle of TSD's. The actual time gating of
the data into the E register from the hus is performed hy the
^ i8a ^ 200;
lOBM — 3 — ► E level. This gating occurs at QK . At QK , a
■ IDO
' -♦■ lOU pulse is generated which clears the STatus flip-flop and
generates the lOCM level.
In a free -running device it is possible that a second word will arrive
at the input buffer before the first word has been transferred into the
computer. In this case^, the second word will take the place of the
first word and the first word will be lost. The MISIWD (mis indication)
level will be geinerated in order to inform the computer and the operator
of the lost line of data.
15-7 ALAEMS
There are three alarm situations associated with the In-Out Element:
1) An lOSAL alarm will occur during an lOS if the M (maintenance) level is present.
The logic for this alarm is shown in Fig. 15-13- Note that the alarm is
2hcc
synchronous and can only occur at PK during an lOS instruction.
2) When a free-running device is being operated, it is possible for the device to
request data transfers by TSD's faster than TSD's are performed by the computer.
The magnetic tape, PETR and BATRAC units have this characteristic. Under these
conditions, the In-Out unit's MISIKD flip-flop will be set. The setting of
MISIKD is synchronized by the lOI clock pulses . The corresponding lOCT
level generated may then cause a MISAL alarm.
^^ISIWD
3) In the third situation, an lOCVT or lOGM level can raise the flag of
the In-Out Alarm. The In-Out Alami Sequence program is not unique and depends
on the particular way in which the programmer desires to handle these alarms.
March I961 15-19
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(OO) STARTOVEE SEQUENCE
The Startover Sequence has several unique features:
1) It has top sequence priority (OO).
2) The sequence is always connected (no C flip-flop).
3) The sequence switch consists of a synchronizer which synchronizes pulses from the
STARTOVER button.
Fig. 15-Start'r Seq-1 shows a block diagram of the Startover Sequence. When the STAETOVER
pushbutton on the console is depressed, it initiates a Li ^ SYN level through the console
control loei'C. Thns is an nQ-imr-Vi-i-r^nrMiol ir n-<=-.nf5-.^Q4-o^ T cs^'o"i --t--;-,t- -• - ^^ -,v-^„-^ -: „„^ ^ ■ ■■ --"-
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As soon as it is permissible, a change of sequence into the Startover Sequence will occur. Note
that during the change of sequence to this sequence the flag of sequence 00 is lowered. Thus,
if the STARTOVER button is pressed again while a STARTOVER sequence program is operating,
another change of sequence to the STARTOVER sequence will occur as soon as the operating pro-
gram dismisses .
March I961 15-STARTOVER (OO)-l
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(kl) IN-OUT ALARM SEQUENCE
A l3lock diagram of the In-Out Alarm system appears In Fig. 15-10 Al Seq-1. This sequence has
several unusual features:
l) It has no STatus flip-flop.
2) The lOCiyr level is always generated as long as the sequence is connected (i.e.^, as
long as C ) .
3) A TSD in this sequence transfers the data shown in Fig. 15-10 Al Seq-2 into the E
register.
MISIND EIA EIA + MISIKD
An lOCtI or lOCM level from any of the sequences shown will cause the lOCM
level to he generated. Note that this level can be generated only hy In-Out units which can
cause an EIA or a MISIND. If the In-Out Alarm Sequence is connected (i.e.^ turned on hy an
, EIA + MISIND I RAISE
lOS 30 000), the synchronized lOCM^ level will generate the I — ► FLAG-
pulse. Since the In-Out Alarm Sequence has a higher priority than nearly all the other
priorities, the computer will quickly change to this sequence. What occurs thereafter depends
on the program for the In-Out Alarm Sequence. If a TSD is included in the program, the status
of the MISIND and EIA flip-flops of all the connected sequence will be transferred to the E
register.
One peculiarity of this sequence is that, once an In-Out unit generates an alarm and raises the
flag of the In-Out Alarm Sequence, no other unit's alarm will raise the flag until the first
alarm is cleared, i.e., the EIA or MISIND flip-flop causing the alarm must be cleared to ZERO.
March I961 15-10 ALARMS (i+l)-l
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(52) PETR
PETR Is a photoelectric paper tape reader. This device uses photoelectric diodes to sense a tape
that has been pimched with 7 possible holes, plus a feed hole. Only 6 of the holes are used to
store the data which is transmitted to the central computer. The seventh hole is used in the
logic that indicates the end of the tape has been reached, i.e., it is used for control ptirposes
only. The feed hole is used to generate the "completion" pulse that is used in the synchronizing
process.
Data Transfer Modes . Data may be transmitted from the PETR buffer to the central ccmputer
in either the normal or assembly modes. It requires six TSD's to pack a 36-bit word in the
central computer when the assembly mode is \ised. Data is never read into the PETR bioffer,
except when the tape is advanced in the forward direction.
Mechanical Tape Transport . Fig. I5-PEER-I shows the major mechanical featiires of the PETR
tape transport system. The tape may be transported in either the REEL or STRIP mode. When
the STRIP mode is used the tape motion is determined entirely by the capstan. In this case
the reel is not used, i.e., the tape is not wound on the reel. The reel clutch is left
disengaged and the brake partially on.
Both capstan and reel assembly are belt driven by a single reversing drive motor as shown
on the figure. Motion of the reel and capstan Is then controlled by individual reel and
capstan magnetic clutch and brake units. The direction of the drive motor is controlled by
the REV flip-flop in the PETR control box.
The drive controls, when the tape is transported in the REEL mode, are designed to prevent
the tape from accumulating slack between the reel and capstan. When the tape is running
"binward" in the steady-state REEL mode, both the capstan eind reel are driven by the motor.
However, when the tape is running in the "forward" direction, the capstan clutch is dis-
engaged and the capstan brake is partially engaged. The effect of the slippage in the
capstan brake is to provide the reel with a light drag load.
Tape Transport Cycle. The basic tape transport cycle \ised in reading a tape into the computer
is as follows:
First, the tape is advanced in the binward (REv ) direction. During this phase, the data
on the tape is sensed, but not gated into the buffer. (See Fig. 15-PETR-2.) When the end
of the tape is reached, on octal 73 character (this is a character without a 7-th hole) is
sensed. The octal 73 is AlilDed with KEY' to generate an End Mark (EM) level. EM is used to
gate a feed-hole transition. EM • <^H ^ then clears the REV flip-flop to ZERO, thus
reversing the direction of the drive motor. The tape now begins running in the forward
direction. Note that if the PETR had not been logically connected, then C • EM • ^CH^]^
would have cleared the CLUTCH flip-flop to ZERO thus stopping the tape motion. Note also
that EM • <^H„^ is not a synchronized signal.
March I961 15-PKrR (52) -1
Each feed hole (H ) that the PETR senses is synchronized "by an lOI clock pulse in the PETR
synchronizer. If the tape is running in the forward direction and a seventh hole is present
on tne uape \h._p ' ruijv j) oncn one vjui.ojju.ij wj. oxxc bj/j.i^j.j.i.vjxj.j./i^j. i,^^^ s>°-"^ ■-'■•■^^ v^ctj^c ^civ^^ ^.liuij
the PETR buffer. The fact that PETR is connected (C ) means that the output of the synchro-
nizer will also be transmitted to the Sequence Selector as a ' ►FLAG „ pulse.
Motion Control Logic. Fig. 15-PETR-2 is a block diagram of the PETR sequence switch and
control unit. Most of the logic found on this figure has been previously described. How-
ever the motion control logic is unique to the PETR and requires explanation.
The motion control logic must be able to run the tape in both the forward and reverse
direction in either the STRIP or REEL mode. In addition, the motion control logic must
take into account the inertia transient effects during tape reversals and run-stop operations.
Fig. 15-PEER-2 shows how this logic is generated. First, a level is generated, indicating
that the computer wants the tape to move. This level is called M . M will not be present
(M ) when the tape is slowing down, prior to stopping or reversing direction. A second
level is generated and used when the tape is operated in the REEL mode and the tape is
traveling in the bin direction. This level is called B.
Consider now how M and B are generated. Whenever the state of the REV flip-flop is changed,
1 "^ 1
a term called VD is generated. This is the output of a variable delay unit. YD will
persist for a predetermined length of time, after which the output of the variable delay
■unit will revert to VD^ . The function of this level (VD, ) is to stop the motion of the
tape while the drive motor is changing its direction. Ass-uming that the unit is connected
(C ) and the Stop Unit level is not present, M will be generated as long as the CLUTCH
flip-flop is set to OWE and the VD level is present. Whenever a transition to M (<CM ^)
occurs, a variable delay level called VDp is generated. This level is similar to VD and
will become VDp after a predetermined length of time. The primary function of VD is to
\ ■ 11
apply the booster brakes when they are needed. Note that VDp occurs whenever VD occurs
1
(that is, during reversal operations), but that VD does not necessarily occur whenever
VD occurs (that is, during CLUTCF" ► CLUTCH or RUM ► STOP operations).
There are two situations which will generate B. If the tape has been traveling in the binward
direction for some time, the REv" • VD-, condition will be satisfied. This is sufficient to
generate B. If the REV flip-flop is suddenly cleared to ZERO while the tape is traveling
in the binward direction, B will persist until the tape actually comes to a stop and reverses
direction. This happens because clearing the REV flip-flop to ZERO initiates VD , and
1 1
REV • VD generates B. Here again, the VD serves as a digital memory for the mechanical
system during the motor reversing period.
15 -PETR (52) -2 March I961
Consider next the logic used in operating the capstan and reel clutches and brakes. In
addition to M and B, another level must be considered. This is the level initiated by the
V
KEEL-STRIP switch on the PETR PB control panel. The S level indicates the STRIP mode, and
the S level indicates the REEL mode.
The presence of S is sufficient to disengage the reel clutch and engage the reel brake. The
actual engagement and disengagement of the capstan clutch and brake occur conversely and, in
the STRIP mode, depend only on M .
When the PETR is operated in the REEL mode, a slightly more complicated drive logic is used.
When the tape is transported binward, the capstsin clutch -will be engaged whenever M is
— 1 ^
present. It will also be engaged during M while VD . The logic that is engaging the capstan
clutch will always be disengaging the capstan brake. The reel clutch is engaged whenever
M is present and, similarly, the reel brake operates whenever M is not present (M ). The
reel brake booster is present only while VDp. Fig. 15-PETR-3 shows the time relationship of
these levels during a typical operating cycle.
MISAL Alarm. Since the PETR is a free-running input device, it has a MISIKD flip-flop.
Fig. 15-PETR-2 shows that the MISIM) flip-flop is cleared to ZERO whenever the device is
connected ( <C"^> ) or the PETR ^^ ♦ IOC level is generated.
The MISIND flip-flop is set under the following circumstances: Suppose that the Raise Flag
signal has just gated data into the PETR buffer. This same Raise Flag signal will set the
STatus flip-flop to ONE. Note that the MISIND flip-flop cannot be set to ONE because the
STatus flip-flop is in the ZERO state when the Raise Flag signal sirrives. If a TSD now
occurs, data will be gated into the E register by an lOBM — j — ^- E pulse at Qlt . The
' ► lOij pulse will then clear the STatus flip-flop at QK and the cycle may be repeated.
However, if another Raise Flag signal occurs before a TSD has read the content of the buffer
into the computer and cleared the STatus flip-flop with a ' ► lOU pulse, the initial content
of the PJi'i'R buffer will become permanently lost. In this case, the STatus flip-flop will be
in the ONE state when the Raise Flag signal arrives. If, in addition, the STOP UNIT level
is absent (STOP UNIT), the MISIND flip-flop will be set to ONE. When this occurs the MISAL
alarm flip-flop in the central computer will be set and, if the In-Out Alarm Sequence is
turned on its flag will be raised-
The reason for including the STOP UNIT level in the ' — *► MISIND logic is as follows: Suppose
that some other sequence (magnetic -tape, for example) generates a MISIND which in turn sets
the MISAL alarm and stops the computer. Even though the computer is stopped, the PETR will
continue to generate Raise Flag signals until the tape can be brought to a stop by the M~
level. If the STOP UNIT level were not included in the ' — ► MISIND logic, it would be
impossible to determine whether the Magnetic-tape Sequence or the PETR Sequence had caused
the original MISAL alarm. The STOP UNIT level inhibits the PETR MISIND flip-flop from being
set in this case.
March I961 15 -PETR (52) -3
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(63) HI SPEED PUNCH
This is an output device which punches holes in paper tape. Six bits of information are
transferred from the central computer to the tape dicing each TSD.
Modes. Any of k possible modes can be selected for punching. In 7-th hole mode a 7-th
hole is punched with each line of data resulting from a TSD.
Normal or assembly mode can also be specified. In the normal mode bits 1.1 through 1.6 of
the register specified by the TSD are pimched in that order on a line of tape with 1.6
going into hole 1. The line can be read as it existed in memory by viewing the tape with
the 7-th hole on the right.
In the assembly mode each line punched is made up of every 6-th bit of the 36 bit word in
memory starting with 1.6, viz. 1.6, 2.3, 2.9, 3.6, h.3 and k.9. After a TSD in this mode
is performed the memory word is cycled one place to the left, so that successive TSD's
referring to the same memory word record different bits of the word even though they are
taken from the same bit positions. In this way a full 36 bit word is disassembled into 6
successive lines of tape. Normal or assembly modes can be used either with or without the
7-th hole mode.
lOS instruction bits which specify modes are as follows:
1.2
1-3
= NORMAL
1 = ASSEMBLY
= 7-th HOLE°
1 = 7-th ho:
ilk'-
The bits in the punch control transmitted to the E register by an lOS report instruction
are as follows:
lOBM. ^ ASSY
BM^
lOBM^ 7-th HOLE
IOBM2 ^ M.C"'- • EIA
lOBM^^g C
lOBM^^^
lOBM^^g
M
ST
Mechanical Punch Cycle . The TSD instruction serves to start the drive motor as well as to
initiate punching. No actual punching can occur, however, until the motor is up to speed.
This involves a delay of about 1 second. The drive motor will continue to run as long as
TSD commands are given at a rate exceeding one every 5 seconds. The motor will stop about
5 seconds after the last TSD command.
March I961 15 -HI SPEED PUNCH (63)-!
The basic mechanical cycle of the punch consists of: (l) pimching the tape with the data
stored in the punch buffer^ and (2) advancing the tape while the buffer is loaded with more
daoa j-rom ohe cenoral computer •
The punching mechanism has two biiilt in pickups which generate "puach" and "feed" sync
signals. The punch sync generates a positive going pulse at the beginning of the punch
cycle and a negative going piilse at the end of the punch cycle. These pulses are identified
as<^START PIINCH^ and <^EKI) PlMCH/> , respectively. Similarly the feed sync generates a
positive going pulse at the beginning of the feed cycle and a negative going pulse at the
end of the feed cycle. These, piolses are identified as <START FEED> and <EKD FEED>
respectively. Since the <^START FEED> and <^E'ND PUWCH^ pulses are essentially coincident,
the •<^EM) PUMCH^ pulse is used to indicate both conditions.
Punch and Feed Control Details. Fig. I5-PUWCH-I is a block diagram of the punch sequence
switch, control box and mechanism. Fig. 15-PUl\rCH-2 shows the time relation of the events
that occur during the punch feed cycle.
Assume that the central computer is in the punch sequence, and the sequence is connected,
but that the punch motor is off. Suppose now that the program calls for a punch TSD.
During the operand cycle (QK) the punch buffer will first be cleared by a ' — ► lOB pulse
I DO
and then a ' ^- lOU pulse will occur. This pulse does several things:
1) It is used in the sequence switch to gate data from the central computer into the
pimch buffer in the specified mode.
2) It clears the STatus flip-flop to ZERO. ST causes the lOCiyr level to be
generated and in so doing tells the central computer the punch b-uffer is now busy.
■ 3) It sets the PUNCH flip-flop to OEE, indicating a punch-feed cycle is to follow.
k) It causes the MOTOR ON level to be generated. This level comes from a variable
delay unit. The I ► lOU pulse starts the variable delay unit timing. After the
preset variable delay, the unit will generate a MOTOR ON level unless in the mean
time another I ^ lOU pulse (or <^FEED ^ ) pulse has reset the variable delay.
Actually two VD units are used to handle the variable delay logic.
The MOTOR ON level causes the motor to begin coming up to rated speed. The punch and feed
sync signals start occurring. However these signals have no effect until the motor is up
/ Ov
to rated speed (oJ ).
The first <^START PLfflCH> sync pulse sets CODE to a OWE (assuming the PUNCH is now set to
ONE and the 1-second MOTOR ON delay has ended). CODE^ permits the data in the buffer to be
punched onto the tape. The <CeND PUNCH^ sync pulse that follows sets the FEED flip-flop
to ONE. FEED causes the tape to be advanced in preparation for the next punch cycle.
15-HI SPEED PUNCH (63) -2 March I961
The ^EMD PUWCH]> sync pulse also clears the CODE flip-flop to ZERO. CODE in turn clears
the PUNCH flip-flop to ZERO.
Finally the asynchronous <^EKD PUNCH^ sync pulse is synchronized in the synchronizer by an
lOI clock piiLse. The output of the synchronizer is then used to set the STatus flip-flop
to a OWE. ST causes the lOCM level to be generated vhich indicates to the central
computer that the punch biiffer is now not busy. The output of the synchronizer also causes
the punch raise flag signal to be generated.
I DO
Suppose now that the program calls for another punch TSD to be executed. Another ' — — ► lOU
pulse is generated during the second TSD operand cycle. The I ^ lOU pulse again sets the
PUNCH flip-flop to ONE and pulses the variable delay unit. Note that the unit is pulsed
before the delay has ended, i.e., the motor is still energized and operating at rated speed.
Finally the <^END FEED^ sync pulse associated with the first TSD occurs. This pulse clears
the FEED flip-flop. The <] START PUNCH> sync pulse again sets the CODE flip-flop to ONE.
The punch -feed cycles repeat in this manner until the program ceases to generate TSD's.
The variable delay units will then time out and the MOTOR ON level will be generated. The
drive motor will now coast to a stop.
Special Control Features. By means of the TAPE FEED switch on the punch panel, the tape
may be advanced independent of the central computer. The TAPE FEED level causes the MOTOR
ON level to be generated. After 1 second has elapsed, to allow the motor to come up to
speed, the <CeND PUWCH^ sync pulse will set the FEED flip-flop to a ONE. The tape will
then be advanced.
Alarms. Alarm circuits have been provided to indicate the presence of conditions requiring
human attention. All alarms will manifest themselves by a buzzer sounding and a red light
turning on. The EIA flip-flop will also set when the next TSD occurs. If the alarm ACK-
RESET switch is now set to ACK, (acknowledge) the buzzer will be suppressed and the red
light and EIA condition will continue as long as the switch remains in this position, even
after the cause of the alarm is corrected. If the alarm condition is corrected and the
switch is turned to RESET, the light will go off, and the buzzer is stopped. However, the
EIA flip-flop can only be cleared by a connection process.
The most common type of alarm results from the amount of tape on the supply reel diminishing
to about 100 feet. This will cause the LOW TAPE level to be generated. However this will
not prevent further punching.
March 1961 15 -HI SPEED PUNCH (63) -3
The following conditions will generate an ALAEM level which will prevent further punching:
1^ If the tape handler ±ail5 oo supp-uy oape oo uhe punch as req_uireu- a swiuCn aoove
the slack loop will sense this and cause an alaarm. This can happen if the b-ulh
providing the light beam burns out. It can also happen if the tape is loaded
improperly, or if the end of the tape roll is reached and is glued securely to
the form. This alarm will inhibit further punching and manual feeding and allow
the motor to stop after 5 second delay. The feed button or a TSD can restart the
motor in this condition but it will not cause punching.
2) The end of the tape passing through the end of tape sensor will create the same
effect as alarm 1 described above. This prevents the very end of the tape, which
is thickened by a paper glued to it, from going into the paunch and jamming it.
3) It is necessary to lubricate the punch after each k hoiirs of running. To prevent
it from being operated for longer intervals without lubrication, a timer is
provided to shut the machine off once this period has elapsed since the last
lubrication. Only maintenance personnel are authorized to reset this timer, which
times out after k-.'i hoirrs.
15-HI SPEED PUNCH (63) -4 March I961
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